• 제목/요약/키워드: Implementation Phase

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전사적 자원관리 시스템 구현의 성공요인: Markus의 단계별 성공요인에 관한 실증분석 (A Study of Success Factors Influencing Each Phase of ERP System Implementation)

  • 이재정
    • 한국정보시스템학회지:정보시스템연구
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    • 제15권2호
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    • pp.153-171
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    • 2006
  • The objective of this research project is empirically investigating factors influencing EPP system implementation based on the degree of volatility of business environment. The results show that computes with low volatility have successfully implement ERP system compared to companies with high volatility. This research project also identified success factors of each phased chartering phase, executive participation sound assessment of business condition, good understanding of ERP system and carefully constructed case are identified as success factors. During project expenditures, participation of various groups, technical resources, prefect and change management are found to be important for successful construction. Trained users, integration of systems, well-designed process and technical and human resource are found to be success factors during shakedown phase. Managers commitment technical infrastructure, system flexibility, and adequate resource for maintenance and renewing system are identified as success factors of onward and upward phase.

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Multi-trade Prefabrication 기법 적용을 위한 기술적 요구사항 분석 (Analysis of Technical Requirement for Implementation of Multi-trade Prefabrication)

  • 장세준;이강
    • 한국건축시공학회:학술대회논문집
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    • 한국건축시공학회 2016년도 춘계 학술논문 발표대회
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    • pp.113-114
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    • 2016
  • This paper proposes a technical requirements analysis of implementation of multi-trade prefabrication. Recently, there has been a rise in the use of prefabrication to minimize on-site work for time reduction to increase productivity. Prefabrication technique is evolved into multi-trade prefabrication combining other trades from single-trade prefabrication. For implementation of new technique, not only itself but complementary techniques have to be prepared. In this paper, MEP corridor rack, a major item of multi-trade prefabrication, was implemented in the test bed and its process was analyzed to find out technical requirements. As a result, comparatively high level of IT technique was required for efficient use of multi-trade prefabrication in design, lifting and construction phase. In design phase, component level of BIM library was needed for manufacturing; and in lifting phase, BIM-based site logistics process was required. Also in construction phase, laser scanning was implemented for gathering shape and geometry of the wall and slab that were attached to multi-trade prefabrication module.

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DFT 연산 FPGA 모들에 기반한 위상 측정 앨고리즘의 구현 (FPGA Implementation of Recursive DFT based Phase Measurement Algorithm)

  • 안병선;김병일;장태규
    • 대한전기학회논문지:시스템및제어부문D
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    • 제54권3호
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    • pp.191-193
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    • 2005
  • This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The proposed algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

패키지된 KU-밴드용 5-비트 위상변위기 설계 및 제작 (Design and Implementation of a Ku-band Packaged 5-bit Phase Shiner)

  • 장우진;형창희;이희태;이경호;송민규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.21-24
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    • 2000
  • This paper introduces the design and implementation of a Ku-band 5-bit monolithic phase shifter with a ceramic package. The 5-bit phase shifter MMIC was designed and fabricated by using GaAs MESFET switches. The packaged phase shifter demonstrates a phase error less than 11.3 $^{\circ}$ RMS and an insertion loss variation less than 1.0㏈ RMS for 13∼15㎓. For all 32 states, an insertion loss is measured to be 12.2${\pm}$2.2㏈, an input return loss more than 5.0㏈, and an output return loss more than 6.2㏈ from 13㎓ to 15㎓. The chip size of the 5-bit phase shifter MMIC is 2.35${\times}$1.65mm$\^$2/ including digital control circuits. The size of the ceramic packaged phase shifter is 7.2${\times}$6.2mm$\^$2/.

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비최소 위상 시스템에서 음재생을 위한 역변환 필터의 구현 (An Implementation of Inverse Filter for Sound Reproduction of Non-Minimum Phase System.)

  • 노경래;이상권
    • 한국소음진동공학회:학술대회논문집
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    • 한국소음진동공학회 2001년도 춘계학술대회논문집
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    • pp.997-1002
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    • 2001
  • This paper describes an implementation of inverse filter using SVD in order to recover the input in multi-channel system. The matrix formulation in SISO system is extended to MIMO system. In time and frequency domain we investigates the inversion of minimum phase system and non-minimum phase system. To execute an effective inversion of non-minimum phase system, SVD is introduced. First of all we computes singular values of system matrix and then investigates the phase property of system. In case of overall system is non-minimum phase, system matrix has one (or more) very small singular value(s). The very small singular value(s) carries information about phase properties of system. Using this property, approximate inverse filter of overall system is founded. The numerical simulation shows potentials in use of the inverse filter.

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Dragon스트림 암호 알고리즘의 하드웨어 구현 (A FPGA Implementation of Stream Cipher Algorithm Dragon)

  • 김헌욱;황기현;이훈재
    • 한국정보통신학회논문지
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    • 제11권9호
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    • pp.1702-1708
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    • 2007
  • Dragon 스트림 암호 알고리즘은 현재 ECRYPT 프로젝트의 일부인 eSTREAM에 참여하여 소프트웨어 분야(Profile 1)의 Phase 1, 2단계를 통과하여 Phase 3단계에 등록된 상태이다. Dragon은 기존의 스트림 암호와 달리 한 개의 워드(32비트)단위의 NLFSR(non-linear feedback shift register)을 사용하고, 128/256 비트의 key와 IV(Initialization Vector)를 입력받아 64비트의 키 수열을 생성하는 키 수열 발생기(Keystream Generator)이다. 본 논문에서는 Dragon 스트림 암호 알고리즘을 Altera사의 Quartus II툴을 이용하여 Cyclone III FPGA 소자(EP2C35F672I8)에 구현 및 타이밍 시뮬레이션을 하였고, 그 결과 111MHz에서 7.1Gbps의 처리량을 보였다.

광대역 5-bit 위상변위기의 설계 및 제작 (Design and Implementation of the Wideband 5-bit Phase Shifter)

  • 전병휘;정영준;이광일;임인성;오승엽
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 I
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    • pp.613-616
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    • 2003
  • This paper describes the design and implementation of wideband 360$^{\circ}$ phase shifter by using I/Q vector method. One of four quadrants was selected by a switching operation and the desired phase value was obtained by varying attenuation level of attenuator located in I/Q path. The minimum phase RMS error of 3.6$^{\circ}$ and the maximum phase RMS error of 25.2$^{\circ}$ were measured over 6~180Hz frequency range. Those characteristics are good enough for the requirement of ECM radar equipment. The phase values can be adjusted by control module.

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Visual Basic과 UML을 사용한 애플리케이션 개발시의 핵심적 단계: 주문처리 업무를 중심으로 (Critical Steps in Building Applications with Visual Basic and UML: Focusing on Order Processing Application)

  • 한용호
    • 산업공학
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    • 제16권2호
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    • pp.268-279
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    • 2003
  • This paper presents critical steps in building client/server application with UML and Visual Basic, which are derived from the implementation case of a typical order processing system. To begin with, we briefly review the software architecture, the diagrams and the object-oriened building process in the UML. In the inception phase, it is critical to define the project charter, to draw use case diagrams, and to construct a preliminary architecture of the application. In the elaboration phase, it is critical to identify classes to be displayed in the class diagram, to develop user interface prototypes for each use case, to construct sequence diagram for each use case, and finally to design an implementation architecture. Steps to construct implementation architecture are given. In the construction phase, it is critical to design both the database and components. Steps to design these components are described in detail. Additionally the way to create the Internet interface is suggested.

Sliding-DFT를 이용한 다채널 위상 측정 FPGA 시스템 (Sliding-DFT based multi-channel phase measurement FPGA system)

  • 어진우;장태규
    • 전기전자학회논문지
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    • 제8권1호
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    • pp.128-135
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    • 2004
  • 본 논문에서는 sliding-DFT에 순환 구현에 기반한 위상 측정 앨고리즘을 제안하였다. 제안한 앨고리즘은 주파수 변이, 누적 잡음, 계수 근사 영향 등의 오차영향에 강인한 특성을 가지도록 설계되었다. DFT 계수의 유한 비트 근사 구현에 의한 위상 오차는 크기 오차에 비해 매우 작게 나타난다. 위상 오차의 혁신적인 감소는 근사 계수가 복소평면 상에서 4사분면상에 대칭적으로 존재함을 이용하여 얻을 수 있다. 제안한 앨고리즘을 시분할 공유 구조에 기반한 4-채널 전력선 위상 측정 시스템을 설계하고 구현하였다. 구현한 시스템의 동작은 실시간으로 host processor 시스템과 다채널 함수 발생기를 통한 test 환경에서 실험적으로 확인하였다. 제안한 앨고리즘의 위상 측정에 있어 정확한 특성과 유한비트 근사 영향에 강인한 특성은 특히, 빠른 처리 속도와 구현의 감소함이 주요 설계 고려사항인 ASIC 이나 microprocessor에 기반의 임베디드 시스템 적용에 중대한 효과를 제공할 수 있을 것이다.

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내부점 선형계획법에서의 최적기저 추출방법의 구현 (On the Implementation of an Optimal Basis Identification Procedure for Interior Point Method)

  • 임성묵;박순달
    • 경영과학
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    • 제17권2호
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    • pp.1-12
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    • 2000
  • In this study, we deals with the implementation of an optimal basis identification procedure for interior point methods. Our implementation is based on Megiddo’s strongly polynomial algorithm applied to Andersen and Ye’s approximate LP construction. Several techniques are explained such as the use of effective indicator for obtaining optimal partition when constructing the approximate LP, the efficient implementation of the problem reduction technique proposed by Andersen, the crashing procedure needed for fast dual phase of Megiddo’s algorithm and the construction of the stable initial basis. By experimental comparison, we show that our implementation is superior to the crossover scheme implementation.

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