• Title/Summary/Keyword: Impedance Tuner

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10-Bit Full-Coverage Impedance Tuner Using a Directional Coupler and PIN Diodes (방향성 결합기 및 핀 다이오드 스위치를 이용한 10 비트 임피던스 튜너)

  • Lee, Dong-Kyu;Lee, Sang-Hyo;Kwon, Young-Woo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.7
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    • pp.698-703
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    • 2007
  • In this paper, a novel impedance tuner using a directional coupler is proposed. The design topology is analyzed by signal flow graph(SFG) and shows advantages compared with conventional single and double stub methods from the view points of easy implementation and wide tuning range, respectively. This impedance tuner consists of ten switches and its $2^{10}$ tuning points are distributed uniformly on the whole Smith chart. The measured maximum magnitude of the reflection coefficient is 0.9. And the fabricated impedance tuner has a wide bandwidth from 1.8 to 2.2 GHz. Using this impedance tuner, we did a load-pull measurement of a power transistor.

A Design of Adaptive Impedance Tuning Circuit for UHF-Band Using λ/4 Transmission Line and π-Network (λ/4 전송 선로와 π-네트워크를 이용한 UHF-대역 적응형 임피던스 정합 회로 설계)

  • Hwang, Soo-Sul;Hong, Sung-Yong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.3
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    • pp.367-376
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    • 2012
  • This paper describes a Adaptive Impedance Tuning Circuit which can be adaptively tuned between circuit's characteristic impedance and the arbitrary load impedance. The Adaptive Impedance Tuning Circuit is consisted of such parts as mismatch sensor, impedance tuner and tuning algorithm. Each parts's design methods proposed in other papers are compared with their advantages and disadvantages. And we propose simple design method for Adaptive Impedance Tuning Circuit using a ${\lambda}/4$ transmission line and ${\pi}$-network. Calculation formulas and selection algorithm from calculated values of a complex load impedance are proposed and simulation using induced calculation formulas and selection algorithm is performed. Simulation results show good agreement with theoretical predictions.

A Study on the Design of Microwave Oscillator Output Matching Circuit Using 3-dB Coupler Tuner (3-dB Coupler Tuner를 이용한 초고주파 발진기의 출력 정합회로 설계에 관한 연구)

  • 이석기;오재석;이영순;김병철
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.9 no.2
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    • pp.171-178
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    • 1998
  • Generally, the output matching circuit has the most influence to the output power of oscillator and existing method for output matching has difficulty for making the optimum output matching circuit because the matching has to be done nearby the infinite impedance area of the Smith Chart. In this paper, it is studied for the output matching circuit of the microwave oscillator to get the maximum output power. The maximum output point can be found by adjusting the position of moving short in the Tuner while the oscillator is operating after connect the 3-dB coupler Tuner to the oscillator without output matching circuit. To design the oscillator for the maximum output power can be done easily with the microstrip line which is realized from the measured S-parameters of Tuner. In compare the oscillator by the existing method with another one by the suggested method in this paper, the first one has 6.45 dBm output power and second one has 9.71 dBm which is 3.26 dBm higher than the first one at the oscillation frequency 1.0338 GHz.

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Two Noise Parameter Measurement Methods Using Spectrum Analyzer and Comparison (스펙트럼 분석기를 이용한 2가지 잡음 파라미터 측정방법과 비교)

  • Lee, Dong-Hyun;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.12
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    • pp.1072-1082
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    • 2015
  • In this paper, we propose two noise parameter measurement methods using spectrum analyzer. First method, we measure a noise correlation matrix using the 6-port network, and we calculate noise parameters using measured a noise correlation matrix. Second method, we directly measure noise figures of the DUT for source impedance changes, and then noise parameters are extracted from the measured noise figures. In order to measure a noise figure, we present a method of measuring a noise figure of the DUT that have arbitrary source impedances using spectrum analyzer and a method of eliminating a noise effect of a impedance tuner. Finally, the noise parameters of a passive and active DUT using proposed two methods are compared. The comparison shows that the two results obtained from for the two methods give almost identical noise parameters. The noise parameters measured by 6-port network accurately predict measured noise figures of the DUT for source impedance changes, and noise parameters measured by 6-port network is verified from the comparison.

Measurement of Noise Parameters Using 6-Port Network (Invited Paper) (6-포트 회로망을 이용한 잡음 파라미터 측정)

  • Yeom, Kyung-Whan;Ahmed, Abdule-Rahman
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.2
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    • pp.119-126
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    • 2015
  • The information about noise parameters is essential in the design of low noise amplifier. In the past, the noise parameters were measured using an impedance tuner and noise figure analyzer. Recently, the authors proposed the method of measuring the noise parameters using the 8-port network without the aid of the mechanically driven impedance tuner. However, the 8-port method still requires the noise source and causes the complexity in the measurements. In this paper, a novel measurement method of the noise parameters without the noise source using 6-port network is proposed. Based on the proposed 6-port method, the noise parameters of 10 dB attenuator whose noise parameters can be theoretically determined were measured and the measured noise parameters are compared with those measured using the previous 8-port network method. As a result, the accuracy of the measured noise parameters using 6-port network is found to be comparable to the previous 8-port network method.

A UHF CMOS Variable Gain LNA with Wideband Input Impedance Matching and GSM Interoperability

  • Woo, Doo Hyung;Nam, Ilku;Lee, Ockgoo;Im, Donggu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.4
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    • pp.499-504
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    • 2017
  • A UHF CMOS variable gain low-noise amplifier (LNA) is designed for mobile digital TV tuners. The proposed LNA adopts a feedback topology to cover a wide frequency range from 474 to 868 MHz, and it supports the notch filter function for the interoperability with the GSM terminal. In order to handle harmonic distortion by strong interferers, the gain of the proposed LNA is step-controlled while keeping almost the same input impedance. The proposed LNA is implemented in a $0.11{\mu}m$ CMOS process and consumes 6 mA at a 1.5 V supply voltage. In the measurement, it shows the power gain of greater than 16 dB, NF of less than 1.7 dB, and IIP3 of greater than -1.7 dBm for the UHF band.

A Design of Amplifier Using Harmonic Termination Impedance Matching Tuner and Bias Line (고조파 차단 특성을 가지는 정합용 튜너와 바이어스 선로를 이용한 증폭기 설계)

  • Lee Jin-Kuk;Kim Su-Tae;Lim Jong-Sik;Jeong Yong-Chae
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.12 s.103
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    • pp.1186-1193
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    • 2005
  • In this paper, a new 3 dB branch line hybrid using asymmetric spiral-shaped defected ground structure(DGS) microstrip is proposed. The proposed branch line hybrid suppresses the 2nd and the 3rd harmonic component effectively. Also a DGS $\lambda$/4 bias line that can suppress high frequency harmonics as well as low frequency intermodulation component is proposed. With the harmonic termination tuner using the proposed hybrid and the harmonic blocking bias line, the 2nd and the 3rd harmonic components of the fabricated amplifier that operated in IMT-2000 basestation transmitting band were suppressed up 25 dB and 27 dB, respectively. The proposed harmonic load-pull setup of amplifier is more easily accomplished with proposed circuits than the previous.

Development of an SIS(Superconductor-Insulator-Superconductor) Junction Mixer over 120∼180 GHz Band (120∼180 GHz 대역 SIS (Superconductor-Insulator-Superconductor) 접합 믹서의 개발)

  • Chung, Moon-Hee;Lee, Changhoon;Kim, Kwang-Dong;Kim, Hyo-Ryoung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.8
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    • pp.737-743
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    • 2004
  • A fixed-tuned SIS(Superconductor-Insulator-Superconductor) mixer across 120∼180 GHz band has been developed. This mixer employs an SIS chip fabricated by Nobeyama radio observatory which consists of a series array of 6 Nb/Al-Al$_2$O$_3$/Nb junctions in a microstrip line on a fused quartz substrate. The SIS chip is placed at the center of the half-height waveguide mixer mount to have a good incoming signal coupling over the whole frequency band. No mechanical tuner was used in the SIS mixer and the RF signal and local oscillator power are injected to the mixer via a cooled cross-guide coupler. In order to prevent the IF signal loss, the If output impedance of the SIS mixer was matched to the 50 $\Omega$ input impedance of the IF chain. Measured double sideband noise temperatures of a receiver using the SIS mixer are 32∼131 K over 120∼180 GHz band. The developed SIS mixer is now in use for radio astronomical observations on the TRAO 14 m radio telescope.

Extraction and Analysis of Dual Gate FET Noise Parameter for High Frequency Modeling (고주파모델링을 위한 이중게이트 FET의 열잡음 파라미터 추출과 분석)

  • Kim, Gue-Chol
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.11
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    • pp.1633-1640
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    • 2013
  • In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

Fabrication and Characteristics of a Varactor Diode for UHF TV Tuner Operated within Low Tuning Voltage (저전압 UHF TV 튜너용 바렉터 다이오드의 제작 및 특성)

  • Kim, Hyun-Sik;Moon, Young-Soon;Son, Won-Ho;Choi, Sie-Young
    • Journal of Sensor Science and Technology
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    • v.23 no.3
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    • pp.185-191
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    • 2014
  • The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.