• KIEE International Transactions on Electrophysics and Applications
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• 제4C권6호
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• pp.272-275
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• 2004

A balanced single side-band (SSB) mixer employing a sub-harmonic configuration is designed for up and down conversions in K-band. The designed mixer uses anti-parallel diode (APD) pairs to effectively eliminate even harmonics of the local oscillator (LO) spurious signal. To reduce the odd harmonics of LO at the RF port, we employ a balanced configuration for LO. The fabricated chip shows 12$\pm$2dB of conversion loss and image-rejection ratio of about 20dB for down conversion at RF frequencies of 24-27.5GHz. As an up-conversion mode, the designed chip shows 12dB of conversion loss and image-rejection ratio of 20 ～ 25 dB at RF frequencies of 25 to 27GHz. The odd harmonics of the LO are measured below -37dBc.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.1663-1667
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• 2003

This thesis is on tile development of LD(Laser Diode) chip tester and the control system based on graphical programming language(LabVIEW) to control the equipment. The LD chip tester is used to test the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the receiver(optic fiber) are very small. Therefore, in order to test each chip precisely, this tester needs high accuracy. However each motion part of the tester could not accomplish hish accuracy due to the limit of the mechanical performance. Hence. an image processing with machine vision was carried out in order to compensate for the error. and also a load test was carried out so as to reduce tile impact of load on chip while the probing motion device is working. The obtained results were within ${\pm}$5$\mu\textrm{m}$ error.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1536-1539
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• 1987

This paper describes the method to extract CIF(Caltech Intermediate Form) by the digital image processing techniques from the VLSI chip. It is possible to represent to the layout editing system. The resolution of the image is 512 512 and 12 bits.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.444-449
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• 1996

The semiconductor, which is precision product, requires many inspection processes. The surface conditions of the semiconductor chip affect on the functions of the semiconductors. The defects of the chip surface are cracks or voids. As general inspection method requires many inspection procedure, the inspection system which searches immediately and precisely the defects of the semiconductor chip surface is required. We suggest the detection algorithm for inspecting the surface defects of the semiconductor surface. The proposed algorithm first regards the semiconductor surface as random texture and point spread function, and secondly presents the character of texture by linear estimation theorem. This paper assumes that the gray level of each pixel of an image is estimated from a weighted sum of gray levels of its neighbor pixels by linear estimation theorem. The weight coefficients are determined so that the mean square error is minimized. The obtained estimation window(two-dimensional estimation window) characterizes the surface texture of semiconductor and is used to discriminate the defects of semiconductor surface.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1272-1273
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• 2009

We demonstrate conformal phosphor coating and patterning methods on light emitting diodes (LEDs) using image processing based optofluidic maskless lithography (IP-OFML) system in microfluidic channels. IP-OFML allows a real-time detection and dynamic mask generation for packaging of randomly dispersed microchips. Our system detects each chip by considering rotation of the chip through image processing regardless of their arrangement error. Therefore, it precisely packages the chip making conformal polymer layer.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 춘계학술대회 논문집
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• pp.641-642
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• 2009

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1041-1044
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• 1998

In this paper the cellular neural networks with annealing capability is designed. The annealing capability helps the networks escape from the local-minimum points and quickly search for the global-minimum point. A 6$\times$6 CNN chip is designed using a $0.8\mu\textrm{m}$ CMOS technology, and the chip area is 2.89mm$\times$2.89mm. The simulation results for hole filling image processing show that the general CNN has a local-minimum problem, but the annealed CNN finds the global-minimum solutions very efficiently.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2007년도 추계학술대회 논문집
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• pp.100-103
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• 2007

A microlens array has been required to improve light conversion efficiency in image sensors. A microlens array can be usually fabricated by photoresist reflow, hot-embossing, micro injection molding, and UV-imprinting. Among these processes, a UV-imprinting, which is operated at room temperature with relatively low applied pressure, can be a desirable process to integrate microlens array on image sensors, because this process provides the components with low thermal expansion, enhanced stability, and low birefringence, furthermore, it is more suitable for mass production of high quality microlens array. In this study, to analyze the optical properties of the wafer scale microlens array integrated image sensor, another wafer scale simulated image sensor chip array was designed and fabricated. An aspherical square microlens was designed and integrated on a simulated image sensor chip array using a UV-imprinting process. Finally, the optical performances were measured and analyzed.

• 대한전자공학회논문지
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• 제26권4호
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• pp.120-126
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• 1989

최근 집적도의 증가와 더불어 집적회로 제작과 점검을 자동화하기 위하여 영상처리방법을 이용한 집적회로의 인식 알고리듬이 개발되고 있다. 집적회로를 인식하기 위해서는 프레임 영상으로 부터 특징을 얻고 이것으로써 칩내의 모든 프레임 영상을 정합하여야한다. 본 논문은 layout 정보를 나타내는 꼭지점들의 위치와 형태를 직선화 알고리듬을 이용하여 추출한다. 부분적으로 겹치는 이웃 프레임들을 얻어진 꼭지점의 위치와 형태를 특징으로 하여 정합함으로써 꼭지점의 전체적 좌표와 형태를 추출한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.491-494
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• 1999

Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. In this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtain a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.