• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.109-116
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• 2003

In this paper. we Propose an UXGA class LCD controller for controlling the LCD panel. The proposed controller supports the full screen display using GCD between input and output resolutions. The proposed LCD controller includes the motion detector based on median filter which can detect the motion of input image for the enhancement of a image quality. Also, it divides the motion into 3 stages such as still, semi-moving and moving, and uses the different interpolation algorithms according to the degree of motion. In order to evaluate the performance of the proposed interpolation algorithm, we use PSNR method and compare the conventional algorithm by using computer simulation. For the proposed motion detection algorithm, we use a visual verification and the estimation of pixel changes. The proposed LCD controller has been designed and verified by VHDL. It has been synthesized using Xilinx VirtexE FPGA.

• Journal of IKEEE
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• v.27 no.4
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• pp.494-500
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• 2023

Image processing is currently used in various fields. Among them, autonomous vehicles, medical image processing, and robot control require fast image processing response speeds. To fulfill this requirement, hardware design for real-time processing is being actively researched. In addition to the size of the input image, the hardware processing speed is affected by the size of the inactive video periods that separate lines and frames in the image. In this paper, we design three different scaler structures based on the type of line memories, which is closely related to the inactive video periods. The structures are designed in hardware using the Verilog standard language, and synthesized into logic circuits in a field programmable gate array environment using Xilinx Vivado 2023.1. The synthesized results are used for frame rate analysis while comparing standard image sizes that can be processed in real time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.8
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• pp.3918-3934
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• 2017

This paper presents a viewport resolution scaling technique to reduce power consumption in mobile graphic processing units (GPUs). This technique controls the rendering resolution of applications in proportion to the resolution factor. In the mobile environment, it is essential to find an effective resolution factor to achieve low power consumption because both the resolution and power consumption of a GPU are in mutual trade-off. This paper presents a resolution factor that can minimize image quality degradation and gain power reduction. For this purpose, software and hardware viewport resolution scaling techniques are applied in the Android environment. Then, the correlation between image quality and power consumption is analyzed according to the resolution factor by conducting a benchmark analysis in the real commercial environment. Experimental results show that the power consumption decreased by 36.96% on average by the hardware viewport resolution scaling technique.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.397-404
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• 2013

This paper propose the hardware architecture of face detection hardware system using the AdaBoost algorithm. The proposed structure of face detection hardware system is possible to work in 30frame per second and in real time. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data by Matlab, and finally detected the face using this data. This paper describes the face detection hardware structure composed of image scaler, integral image extraction, face comparing, memory interface, data grouper and detected result display. The proposed circuit is so designed to process one point in one cycle that the prosed design can process full HD($1920{\times}1080$) image at 70MHz, which is approximate $2316087{\times}30$ cycle. Furthermore, This paper use the reducing the word length by Overflow to reduce memory size. and the proposed structure for face detection has been designed using Verilog HDL and modified in Mentor Graphics Modelsim. The proposed structure has been work on 45MHz operating frequency and use 74,757 LUT in FPGA Xilinx Virtex-5 XC5LX330.

• Annual Conference of KIPS
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• 2007.05a
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• pp.293-296
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• 2007

필드 워핑은 상대적으로 많은 연산량을 요구하는 것에 반해 제어선을 이용하여 워핑 결과를 좀 더 세밀하게 제어할 수 있는 것이 장점이다. 필드 영상 워핑 및 모핑의 동작 특성상, 국부적인 영상 확대와 축소 및 회전 등과 같은 다양한 기하학적인 변형이 복합적으로 발생하게 되는데 역방향 매핑 과정에서 소스 영상과 목적 영상의 화소가 정수 화소 단위로 대응되지 않을 경우, 목적 영상에 대응시킬 화소값을 산출하기 위해 적합한 영상 보간 기술이 필요하다. 다양한 보간 기술들 중에서 평균적으로 우수한 결과를 제공하는 양선형 보간이 보편적으로 사용되고 있으나, 이 보간 기술은 대각선 방향의 윤곽선 재현에 한계를 가지고 있다. 본 논문은 필드 워핑과 모핑을 위한 pseudomedian 필터 기반 영상보간법을 제안하고 주관적인 화질을 분석 평가함에 그 목적이 있다. 제안된 보간 방법은 양선형 보간과 윤곽선 재현에 우수한 특성을 보이는 pseudomedian 필터 보간을 효과적으로 결합한 것이다. 제안된 방법에 따르면 다른 보간 기법에 비해 상대적으로 자연스러운 워핑 및 모핑 결과를 얻을 수 있다. 제안된 방법의 타당성과 보편성을 검증하기 위해 서로 다른 분포 특성을 갖는 영상을 대상으로 주간적인 화질 측면에서 그 성능을 분석 평가하였다.

• The korean journal of orthodontics
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• v.26 no.5 s.58
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• pp.613-622
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• 1996

The purposes of this study were to evaluate and compare the frequency of ceramic bracket fracture, frequency of enamel fracture, bond fracture site, adhesive remnant index after mechanical and electrothermal debracketing, to evaluate effectiveness of high and low speed rotary instrument and ultrasonic instrument during residual adhesive remnants removal, and to measure resin film surface(percentage) using by image analyser(Leco 300). Bond fracture site, bracket fracture, and enamel surface damage were examined by scanning electron microscope. The following results were obained : 1. In the mechanical debracketing group, the bond failed predominantly at enamel-adhesive interface with the bulk of adhesive remaining on bracket base. 2. In the eletrothermal debracketing group, the bond failed predominantly at adhesive-bracket interface with the bulk of adhesive remaining on enamel surface. 3. The most effectiveness of residual resin removal was obtained by means of the resin polishing bur and the order of scratch formation was the procedure using tungsten carbide bur, ultrasonic scaler, sof-lex disc, and polishing bur. 4. The order of the resin film surface percentage was ultrasonic scaler, tungsten carbide bur, sof-lex disc, and resin polishing bur.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.2
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• pp.33-44
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• 2010

This paper propose the structure of real-time face detection hardware architecture for robot vision processing applications. The proposed architecture is robust against illumination changes and operates at no less than 60 frames per second. It uses Modified Census Transform to obtain face characteristics robust against illumination changes. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data, and finally detected the face using this data. This paper describes the face detection hardware structure composed of Memory Interface, Image Scaler, MCT Generator, Candidate Detector, Confidence Comparator, Position Resizer, Data Grouper, and Detected Result Display, and verification Result of Hardware Implementation with using Virtex5 LX330 FPGA of Xilinx. Verification result with using the images from a camera showed that maximum 32 faces per one frame can be detected at the speed of maximum 149 frame per second.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.4
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• pp.116-128
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• 2011

In this paper, we propose the structure of a high-performance face-detection engine that responds well to facial rotating changes using rotation transformation which minimize the required memory usage compared to the previous face-detection engine. The validity of the proposed structure has been verified through the implementation of FPGA. For high performance face detection, the MCT (Modified Census Transform) method, which is robust against lighting change, was used. The Adaboost learning algorithm was used for creating optimized learning data. And the rotation transformation method was added to maintain effectiveness against face rotating changes. The proposed hardware structure was composed of Color Space Converter, Noise Filter, Memory Controller Interface, Image Rotator, Image Scaler, MCT(Modified Census Transform), Candidate Detector / Confidence Mapper, Position Resizer, Data Grouper, Overlay Processor / Color Overlay Processor. The face detection engine was tested using a Virtex5 LX330 FPGA board, a QVGA grade CMOS camera, and an LCD Display. It was verified that the engine demonstrated excellent performance in diverse real life environments and in a face detection standard database. As a result, a high performance real time face detection engine that can conduct real time processing at speeds of at least 60 frames per second, which is effective against lighting changes and face rotating changes and can detect 32 faces in diverse sizes simultaneously, was developed.