• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.201-207
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• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.41-50
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• 1999

In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.397-404
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• 2003

Dedicated-purpose embedded Java system usually takes such model that all class files are converted into a single ROM Image by the ROMizer in the host computer, and then the Java virtual machine in the embedded system executes the image. Defining the ROM Image is a very important issue for embedded system with limited memory resource and low-performance processor since the format directly influences on the memory usage and effectiveness of accessing entries in classes. In this paper we have analyzed the ROMizer and especially the format of the ROM image implemented in the simpleRTJ embedded Jana virtual machine. The analysis says that memory space can be saved up to 50% compared to the original class file and access speed exceeds up to six times with the use of the ROMizer. The result of this study will be applied to develop a more efficient ROMizer for a ROM-based embedded Java system.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.4 s.316
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• pp.27-34
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• 2007

In this paper device driver for camera capture in hand held mobile system is implemented based on microsoft windows CE operating system. We also study the storage device driver based on the FAT fie system by using NAND flash memory as a storage device. We use the MBA2440 PDA board for implementing the hardware for image capture by using CMOS camera module producted by PixelPlus company. This camera module has VGA $640{\times}480$ pixel resolution. We also make application program which can be cooperated with the device driver for testing its performance, for example image capture speed and quality of captured image. We check that the application can be cooperated well not only with the device driver for camera capture but also with the device driver for FAT file system designed especially for the NAND flash memory.

• Journal of Broadcast Engineering
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• v.28 no.1
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• pp.42-54
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• 2023

It is an important issue to compress huge holographic data in a digital format. In particular, research on the compression of phase-only holograms for commercialization is noteworthy. Conventional video coding standards optimized for natural images are not suitable for compressing phase signals, and neural network-based compression model that can be optimized for phase signals can achieve high performance, but has a memory issue in learning high-resolution holographic data. In this paper, we show that by applying a block-based learned image compression model that can solve memory problems to phase-only holograms, the proposed method can demonstrate significant performance improvement over standard codecs even under the same conditions as block-based. Block-based learned compression model can provide compatibility with conventional standard codecs, solve memory problems, and can perform significantly better against phase-only hologram compression.

• International Journal of Computer Science & Network Security
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• v.23 no.3
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• pp.177-186
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• 2023

Hyperspectral imaging technology is one of the most efficient and fast-growing technologies in recent years. Hyperspectral image (HSI) comprises contiguous spectral bands for every pixel that is used to detect the object with significant accuracy and details. HSI contains high dimensionality of spectral information which is not easy to classify every pixel. To confront the problem, we propose a novel RGB channel Assimilation for classification methods. The color features are extracted by using chromaticity computation. Additionally, this work discusses the classification of hyperspectral image based on Domain Transform Interpolated Convolution Filter (DTICF) and 3D-CNN with Bi-directional-Long Short Term Memory (Bi-LSTM). There are three steps for the proposed techniques: First, HSI data is converted to RGB images with spatial features. Before using the DTICF, the RGB images of HSI and patch of the input image from raw HSI are integrated. Afterward, the pair features of spectral and spatial are excerpted using DTICF from integrated HSI. Those obtained spatial and spectral features are finally given into the designed 3D-CNN with Bi-LSTM framework. In the second step, the excerpted color features are classified by 2D-CNN. The probabilistic classification map of 3D-CNN-Bi-LSTM, and 2D-CNN are fused. In the last step, additionally, Markov Random Field (MRF) is utilized for improving the fused probabilistic classification map efficiently. Based on the experimental results, two different hyperspectral images prove that novel RGB channel assimilation of DTICF-3D-CNN-Bi-LSTM approach is more important and provides good classification results compared to other classification approaches.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.618-629
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• 2007

In this paper, we propose an effective memory test environment, called a virtualized kernel, for 64bit multi-core computing environments. The term of effectiveness means that we can test all of the physical memory space, even the memory space occupied by the kernel itself, without rebooting. To obtain this capability, our virtualized kernel provides four mechanisms. The first is direct accessing to physical memory both in kernel and user mode, which allows applying various test patterns to any place of physical memory. The second is making kernel virtualized so that we can run two or more kernel image at the different location of physical memory. The third is isolating memory space used by different instances of virtualized kernel. The final is kernel hibernation, which enables the context switch between kernels. We have implemented the proposed virtualized kernel by modifying the latest Linux kernel 2.6.18 running on Intel Xeon system that has two 64bit dual-core CPUs with hyper-threading technology and 2GB main memory. Experimental results have shown that the two instances of virtualized kernel run at the different location of physical memory and the kernel hibernation works well as we have designed. As the results, the every place of physical memory can be tested without rebooting.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.731-734
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• 1998

A scalable parallel algorithm is proposed for efficient image component labeling with local operatos on a mesh connected SIMD computer. In contrast to the conventional parallel labeling algorithms, where a single pixel is assigned to each PE, the algorithm presented here is scalable and can assign m$\times$m pixel set to each PE according to the input image size. The assigned pixel set is converted to a single pixel that has representative value, and the amount of the required memory and processing time can be highly reduced. For N$\times$N image, if m$\times$m pixel set is assigned to each PE of P$\times$P mesh, where P=N/m, the time complexity due to the communication of each PE and the computation complexity are reduced to O(PlogP) bit operations and O(P) bit operations, respectively, which is 1/m of each of the conventional method. This method also diminishes the amount of memory in each PE to O(P), and can decrease the number of PE to O(P2) =Θ(N2/m2) as compared to O(N2) of conventional method. Because the proposed parallel labeling algorithm is scalable, we can adapt to the increase of image size without the hardware change of the given mesh connected SIMD computer.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.999-1002
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• 2003

In this study, embodied supervisory system that apply motion detection technique to small web camera and detects watch picture. Motion detection technique that use pixel value of car image that use in existing need memory to store background image. Also, there is sensitive shortcoming at increase of execution time by data process of pixel unit and noise. Suggested technique that compare extracting motion information by block unit to do to have complexion that solve this shortcoming and is strong at noise. Because motion information by block compares block characteristic value of image without need frame memory, store characteristic cost by block of image. Also, can get effect that reduce influence about noise and is less sensitive to flicker etc.. of camera more than motion detection that use pixel value in process that find characteristic value by block unit.