• Title/Summary/Keyword: Image Comparator

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Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

  • Kwen, Hyeunwoo;Kim, Sang-Hwan;Lee, Jimin;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.29 no.2
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    • pp.82-88
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    • 2020
  • In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

CMOS Binary Image Sensor Using Double-Tail Comparator with High-Speed and Low-Power Consumption

  • Kwen, Hyeunwoo;Jang, Junyoung;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.30 no.2
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    • pp.82-87
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    • 2021
  • In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

Design of a Comparator with Improved Noise and Delay for a CMOS Single-Slope ADC with Dual CDS Scheme (Dual CDS를 수행하는 CMOS 단일 슬로프 ADC를 위한 개선된 잡음 및 지연시간을 가지는 비교기 설계)

  • Heon-Bin Jang;Jimin Cheon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.6
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    • pp.465-471
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    • 2023
  • This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

CMOS Binary Image Sensor with Gate/Body-Tied PMOSFET-Type Photodetector for Low-Power and Low-Noise Operation

  • Lee, Junwoo;Choi, Byoung-Soo;Seong, Donghyun;Lee, Jewon;Kim, Sang-Hwan;Lee, Jimin;Shin, Jang-Kyoo;Choi, Pyung
    • Journal of Sensor Science and Technology
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    • v.27 no.6
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    • pp.362-367
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    • 2018
  • A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

CMOS Image Sensor with Dual-Sensitivity Photodiodes and Switching Circuitfor Wide Dynamic Range Operation

  • Lee, Jimin;Choi, Byoung-Soo;Bae, Myunghan;Kim, Sang-Hwan;Oh, Chang-Woo;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.26 no.4
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    • pp.223-227
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    • 2017
  • Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

Design of Connectivity Test Circuit for a Direct Printing Image Drum

  • Jung, Seung-Min
    • Journal of information and communication convergence engineering
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    • v.6 no.1
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    • pp.43-46
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    • 2008
  • This paper proposes an advanced test circuit for detecting the connectivity between a drum ring of laser printer and PCB. The detection circuit of charge sharing is proposed, which minimizes the influences of internal parasitic capacitances. The test circuit is composed of precharge circuit, analog comparator, level shifter. Its functional operation is verified using $0.6{\mu}m$ 3.3V/40V CMOS process parameter by HSPICE. Access time is100ns. Layout of the drum contact test circuit is $465{\mu}m\;{\times}\;117{\mu}m$.

Image Edge Detector Based on a Bump Circuit and the Neighbor Pixels (Bump 회로와 인접픽셀 기반의 이미지 신호 Edge Detector)

  • Oh, Kwang-Seok;Lee, Sang-Jin;Cho, Kyoungrok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.149-156
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    • 2013
  • This paper presents a hardware edge detector of image signal at pixel level of CMOS image sensor (CIS). The circuit detects edges of an image based on a bump circuit combining with the pixels. The APS converts light into electrical signals and the bump circuit compares the brightness between the target pixel and its neighbor pixels. Each column on CIS 64 by 64 pixels array shares a comparator. The comparator decides a peak level of the target pixel comparing with a reference voltage. The proposed edge detector is implemented using 0.18um CMOS technology. The circuit shows higher fill factor 34% and power dissipation by 0.9uW per pixel at 1.8V supply.

CMOS binary image sensor with high-sensitivity metal-oxide semiconductor field-effect transistor-type photodetector for high-speed imaging

  • Jang, Juneyoung;Heo, Wonbin;Kong, Jaesung;Kim, Young-Mo;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.30 no.5
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    • pp.295-299
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    • 2021
  • In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.

Image Edge Detector Based on Analog Correlator and Neighbor Pixels (아날로그 상관기와 인접픽셀 기반의 영상 윤곽선 검출기)

  • Lee, Sang-Jin;Oh, Kwang-Seok;Nam, Min-Ho;Cho, Kyoungrok
    • The Journal of the Korea Contents Association
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    • v.13 no.10
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    • pp.54-61
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    • 2013
  • This paper presents a simplified hardware based edge detection circuit which is based on an analog correlator combining with the neighbor pixels in CMOS image sensor. A pixel element of the edge detector consists of an active pixel sensor and an analog correlator circuit which connects two neighbor pixels. The edge detector shares a comparator on each column that the comparator decides an edge of the target pixel with an adjustable reference voltage. The circuit detects image edge from CIS directly that reduces area and power consumption 4 times and 20%, respectively, compared with the previous works. And also it has advantage to regulate sensitivity of the edge detection because the threshold value is able to control externally. The fabricated chip has 34% of fill factor and 0.9 ${\mu}W$ of power per a pixel under 0.18 ${\mu}m$ CMOS technology.

A Study of a High Performance Capacitive Sensing Scheme Using a Floating-Gate MOS Transistor

  • Jung, Seung-Min
    • Journal of information and communication convergence engineering
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    • v.10 no.2
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    • pp.194-199
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    • 2012
  • This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.