• Journal of IKEEE
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• v.19 no.2
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• pp.168-175
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• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.152-159
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• 2004

In this study, we design the one-chip PWM IC with high voltage power switch (300V class LDMOSFET) for SMPS (Switching Mode Power Supply) application. Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain $({\simeq}65dB)$, unity frequency $({\simeq}190kHz)$ and large $PM(75^{\circ})$. comparator is designed with 2 stage. Saw tooth generators operate with 20kHz oscillation frequency. Also, we optimize drift concentration & drift length of n-LDMOSFET for design of high voltage switching device. It is shown that simulation results have the breakdown voltage of 350V. (using ISE-TCAD Simulation tool). PWM IC with power switching device is designed with 2um design rule and Bi-DMOS technology.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.25 no.6
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• pp.386-393
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• 2013

After the 2011 Tohoku Earthquake, it has been pointed out that Tokai, Tonankai and Nankai massive earthquakes with a magnitude of 9.0 could strike the Pacific coasts in western Japan. This study aims at investigating numerically propagation characteristics of tsunami generated by a 9.0 magnitude Tokai, Tonankai and Nankai massive earthquakes on the Pacific coasts and three major bays in Japan, Tokyo Bay, Ise Bay and Osaka Bay. It was revealed from the numerical results that the tsunami heights on the Pacific coasts for M9.0 earthquake were about twice as much as those for M8.7 earthquake and the first tsunami arrival time was faster at some areas distant from the tsunami source. Moreover, high water level in the bays was recognized to continue for a long time because of the enclosed bays.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.20 no.1
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• pp.128-136
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• 2008

Recently, the unusual climate change is happening from the global warming in the whole world, the Korean peninsula is also no exception. It is predicted by many researchers that, in the near future, the Super-Typhoon of overwhelming power will occur due to rising temperatures on the sea surface around the Korean peninsula. In this study, numerical simulation has been performed with the Super-Typhoons which combined route of Typhoon Maemi with typhoon conditons of Hurricane Katrina (New Oleans in U.S.A, 2005), Typhoon Durian (philippine, 2006) and Typhoon Vera (Ise Bay in Japan, 1959) at Busan and Gyeongnam coastal area which has been badly damaged due to storm surge every year. From the numerical results, it is revealed that the storm surge heights of the Super-Typhoons are higher than that of Maemi, specially the storm surge height in the case of Katrina is about 4 times larger. So, it can be pointed out that the construction of countermeasures against disasters are very important in order to prepare against an attack of the Super-Typhoons.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.12
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• pp.2213-2220
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• 2017

This paper proposes an efficient approach for hardware implementation of moving object detection (MOD) processor using effective Gaussian mixture learning (EGML)-based background subtraction method. Arithmetic units used in background generation were implemented using LUT-based approximation to reduce hardware complexity. Hardware resources used for both background subtraction and Gaussian probability density calculation were shared. The MOD processor was verified by FPGA-in-the-loop simulation using MATLAB/Simulink. The MOD performance was evaluated by using six types of video defined in IEEE CDW-2014 dataset, which resulted the average of recall value of 0.7700, the average of precision value of 0.7170, and the average of F-measure value of 0.7293. The MOD processor was implemented with 882 slices and block RAM of $146{\times}36kbits$ on Virtex5 FPGA, resulting in 60% hardware reduction compared to conventional design based on EGML. It was estimated that the MOD processor could operate with 75 MHz clock, resulting in real-time processing of $800{\times}600$ video with a frame rate of 39 fps.