• Title/Summary/Keyword: IPS system

Search Result 270, Processing Time 0.024 seconds

Propulsion System of R.O.K.N Warships & Future of Propulsion System (대한민국 해군 군함의 추진체계와 미래의 추진체계 발전방안 연구)

  • Shin, Seungmin;Park, Jong-hwa;Hong, Yong-pyo;Oh, Kyungwon
    • Journal of the Korean Society of Propulsion Engineers
    • /
    • v.25 no.6
    • /
    • pp.53-59
    • /
    • 2021
  • The ROK Navy operates many war ships despite its short history. Various types of war ships, such as submarines, destroyers, frigates, corvette etc., use suitable propulsion systems for the operational requirements of each war ship. A hybrid propulsion system was introduced to change from the current mechanical propulsion system to an electric propulsion system according to the changing patterns of naval warfare, and it is expected that an integrated electric propulsion system will also be introduced. Therefore, this paper investigates the propulsion system of major ships operated by the Korean Navy, predicts the changes in future naval warfare, and proposes a propulsion system for future ships.

Hardware Implementation of DCT and CAVLC for H.264/AVC based on Co-design (병행설계를 이용한 H.264/AVC의 DCT 및 CAVLC 하드웨어 구현)

  • Wang, Duck-Sang;Seo, Seok-Yong;Ko, Hyung-Hwa
    • Journal of Advanced Navigation Technology
    • /
    • v.17 no.1
    • /
    • pp.69-79
    • /
    • 2013
  • In this paper, DCT(Discrete Cosine Transform) and CAVLC(Context Adaptive Variable Length Coding) are co-designed as hardware IP with software operation of the other modules in H.264/AVC codec. In order to increase the operation speed, a new method using SHIFT table is proposed. As a result, enhancement of about 16(%) in the operation speed is obtained. Designed Hardware IPs are downloaded into Virtex-4 FX60 FPGA in the ML-410 development board and H.264/AVC encoding is performed with Microblaze CPU implemented in FPGA. Software modules are developed from JM13.2 to make C code. In order to verify the designed Hardware IPs, Modelsim program is used for functional simulation. As a result that all Hardware IPs and software modules are downloaded into the FPGA, improvement of processing speed about multiples of 16 in case of DCT hardware IP and multiples of 10 in case of CAVLC compared with software-only processing. Although this paper deals with co-design of H/W and S/W for H.264, it can be utilized for the other embedded system design.

Proposal of Security Orchestration Service Model based on Cyber Security Framework (사이버보안 프레임워크 기반의 보안 오케스트레이션 서비스 모델 제안)

  • Lee, Se-Ho;Jo, In-June
    • The Journal of the Korea Contents Association
    • /
    • v.20 no.7
    • /
    • pp.618-628
    • /
    • 2020
  • The purpose of this paper is to propose a new security orchestration service model by combining various security solutions that have been introduced and operated individually as a basis for cyber security framework. At present, in order to respond to various and intelligent cyber attacks, various single security devices and SIEM and AI solutions that integrate and manage them have been built. In addition, a cyber security framework and a security control center were opened for systematic prevention and response. However, due to the document-oriented cybersecurity framework and limited security personnel, the reality is that it is difficult to escape from the control form of fragmentary infringement response of important detection events of TMS / IPS. To improve these problems, based on the model of this paper, select the targets to be protected through work characteristics and vulnerable asset identification, and then collect logs with SIEM. Based on asset information, we established proactive methods and three detection strategies through threat information. AI and SIEM are used to quickly determine whether an attack has occurred, and an automatic blocking function is linked to the firewall and IPS. In addition, through the automatic learning of TMS / IPS detection events through machine learning supervised learning, we improved the efficiency of control work and established a threat hunting work system centered on big data analysis through machine learning unsupervised learning results.

A Novel Architecture for Real-time Automated Intrusion Detection Fingerprinting using Honeypot

  • Siddiqui, Muhammad Shoaib;Hong, Choong-Seon
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2007.05a
    • /
    • pp.1093-1095
    • /
    • 2007
  • As the networking and data communication technology is making progress, there has been an augmented concern about the security. Intrusion Detection and Prevention Systems have long being providing a reliable layer in the field of Network Security. Intrusion Detection System works on analyzing the traffic and finding a known intrusion or attack pattern in that traffic. But as the new technology provides betterment for the world of the Internet; it also provides new and efficient ways for hacker to intrude in the system. Hence, these patterns on which IDS & IPS work need to be updated. For detecting the power and knowledge of attackers we sometimes make use of Honey-pots. In this paper, we propose a Honey-pot architecture that automatically updates the Intrusion's Signature Knowledge Base of the IDS in a Network.

  • PDF

An optimization of synchronous pipeline design for IP-based H.264 decoder design (IP기반 H.264 디코더 설계를 위한 동기화 파이프라인 최적화)

  • Ko, Byung-Soo;Kong, Jin-Hyeung
    • Proceedings of the IEEK Conference
    • /
    • 2008.06a
    • /
    • pp.407-408
    • /
    • 2008
  • This paper presents a synchronous pipeline design for IP-based H.264 decoding system. The first optimization for pipelining aims at efficiently resolving the data dependency due to motion compensation/intra prediction feedback data flow in H.264 decoder. The second one would enhance the efficiency of execution per each pipelining stage to explore the optimized latency and stage number. Thus, the 3 stage pipeline of CAVLD&ITQ|MC/IP&Rec.|DF is obtained to yield the best throughput and implementation. In experiments, it is found that the synchronous pipelined H.264 decoding system, based on existing IPs, could deal with Full HD video at 125.34MHz, in real time.

  • PDF

A design technology for re-configurable MPU and software on FPGA

  • Araki, H.;Harashima, K.;Kutsuwa, T.
    • Proceedings of the IEEK Conference
    • /
    • 2002.07b
    • /
    • pp.936-939
    • /
    • 2002
  • FPCA is the necessary device to design of hardware at present, it is researched on many ways of applying to design caused by expansion of capacity in recent years. One of these applying ways is SoC (System on a Chip) that is proposed for realizing the basic function of a system. For realizing SoC efficiently, IP (Intellectual property) is very important and developed for re-use of hardware. A MPU for built-in exists as an IP. But almost of MPUs at present as an IPs are lengthy and large-scale for using embedded-application. Furthermore, the function of executing specific treatment critically is required to embedded MPU. We propose a flexible and small scale MPU and its design method.

  • PDF

A Case Study on the Application and History of Stuts System using the Underground Excavation Construction (지하굴착공사에 적용되는 버팀 시스템의 변화와 적용 사례연구)

  • Lee, Jung-Jae;Jung, Kyoung-Sik;Roh, Bae-Young;Kim, Hong-Taek
    • 기술발표회
    • /
    • s.2006
    • /
    • pp.54-65
    • /
    • 2006
  • Since timbering of a cut in association with underground excavtion work is introduced to domestic, in spite of limitation of special quality in this method, time change, variety of construction, Strut Method is still considered with general methods. Experts have developed methods which is improved in limitation of special quality by continuous studies of normal strut method in basic, and it has been applied to construction site Consequently, this study introduced improved Strut Method to help experts when they select resonable methods with regard to construction site, conditions

  • PDF

Esthetic restoration of anterior dentition using Empress 2 system: A clinical report

  • Kim, Min-Ho;Yang, Jae-Ho
    • The Journal of Korean Academy of Prosthodontics
    • /
    • v.38 no.6
    • /
    • pp.821-828
    • /
    • 2000
  • Metal - ceramic restorations have been the standard of fixed oral rehabilitation for over 30 years, and while many advances have been made in materials and research, the esthetic challenges of the light reflective metal substructure will always put clinician in an esthetic dilemma, for only a very talented ceramist / dentist team can create esthetics that rival nature on a repeatable basis. All ceramic restorations have also been a choice in our restorative armamentarium, but in the past, the materials have also had their own limitation, number on being question-able strength to withstand occlusal forces generated during mastication. IPS Empress 2 offers dentistry a metal free alternative to traditional restorative techniques. This clinical report describes the treatment of patients with esthetic problem of anterior dentition using Empress 2 system.

  • PDF

Conceptual design of light bascule bridge

  • Xu, Weiwei;Ding, Hanshan;Lu, Zhitao
    • Structural Engineering and Mechanics
    • /
    • v.29 no.4
    • /
    • pp.381-390
    • /
    • 2008
  • This paper proposed a conceptual design of bascule bridge, which is a new kind of movable bridge with an aim of reducing the weight of superstructure. Compared with the traditional bascule bridge, the light bascule bridge chooses cable-stayed bridge with inclined pylon as its superstructure; therefore, the functions of balance-weight and structure will fuse into one. Otherwise, it adopts moving counterweight to adjust its center of gravity (CG) to open or close the bridge. In order to lighten the superstructure, it uses contact springs to auxiliary retract, and intelligent prestressing system (IPS) to control the main girder's deformation. Simultaneously the vibration control scheme of structure is discussed. Starting from establishing the mechanical model of bridge, this article tries to analyze the conditions that the design parameters of structure and attachments should satisfy to. After the design procedure was presented, an example was also adopted to explain the primary design process of this kind bridge.

FPGA-Based Design of Black Scholes Financial Model for High Performance Trading

  • Choo, Chang;Malhotra, Lokesh;Munjal, Abhishek
    • Journal of information and communication convergence engineering
    • /
    • v.11 no.3
    • /
    • pp.190-198
    • /
    • 2013
  • Recently, one of the most vital advancement in the field of finance is high-performance trading using field-programmable gate array (FPGA). The objective of this paper is to design high-performance Black Scholes option trading system on an FPGA. We implemented an efficient Black Scholes Call Option System IP on an FPGA. The IP may perform 180 million transactions per second after initial latency of 208 clock cycles. The implementation requires the 64-bit IEEE double-precision floatingpoint adder, multiplier, exponent, logarithm, division, and square root IPs. Our experimental results show that the design is highly efficient in terms of frequency and resource utilization, with the maximum frequency of 179 MHz on Altera Stratix V.