• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1405-1408
• /
• 2005

An embedded system has been applied to many fields including households and industrial sites. In the past, user interface products with simple functions were commercialized .but now user demands are increasing and the system has more various applicable fields due to a high penetration rate of the Internet. Therefore, the demand for embedded system is tend to rise In this paper, we Implementation of an embedded system for image tracking. This system is used a fixed IP for the reliable server operation on TCP/IP networks. A real time broadcasting of video image on the internet was developed by using an USB camera on the embedded Linux system. The digital camera is connected at the USB host port of the embedded board. all input images from the video camera is continuously stored as a compressed JPEG file in a directory at the Linux web-server. And each frame image data from web camera is compared for measurement of displacement Vector. That used Block matching algorithm and edge detection algorithm for past speed. And the displacement vector is used at pan/tilt motor control through RS232 serial cable. The embedded board utilized the S3C2410 MPU Which used the ARM 920T core form Samsung. The operating system was ported to embedded Linux kernel and mounted of root file system. And the stored images are sent to the client PC through the web browser. It used the network function of Linux and it developed a program with protocol of the TCP/IP.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.9
• /
• pp.373-383
• /
• 2003

In this paper we discuss the effect of the delay limit and the packet size related to the quality of service on a VoIP system using the Internet. We also provide a guideline to determining the optimal packet size of the voice data for a given delay limit. Empirical studies are done with two personal computers connected through the packet switched public IP network. The sender encodes the voice signal from the microphone to get PCM and ADPCM data and sends the data to the receiver using UDP packets. The receiver plays the reconstructed voice from the stream with lost and delayed packets. The quality of the reconstructed voice is evaluated offline by the MNB (Measuring Normal Block) method using the data acquired from the both sides. The result shows that under the delay limit of 100ms for 40Kbps, 32Kbps and l6Kbps of ADPCM data, the minimum packet size should be 300bytes, 400bytes and 600bytes respectively and the maximum packet size should be l200bytes commonly for the best quality of voice.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.2
• /
• pp.305-311
• /
• 2010

iATA (Internet Advanced Technology Attachment) is a block-level protocol developed to transfer ATA commands over TCP/IP network, as an alternative network storage solution to address insufficient storage problem in mobile devices. This paper employs RAID5 distributed storage servers concept into iATA, in which the idea behind is to combine several machines with relatively inexpensive disk drives into a server array that works as a single virtual storage device, thus increasing the reliability and speed of operations. In the case of one machine failed, the server array will not destroy immediately but able to function in a degradation mode. Meanwhile, information can be easily recovered by using boolean exclusive OR (XOR) logical function with the bit information on the remaining machines. We perform I/O measurement and benchmark tool result indicates that additional fault tolerance feature does not delay read/write operations with reasonable file size ranged in 4KB-2MB, yet higher data integrity objective is achieved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2019.05a
• /
• pp.251-253
• /
• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.199-203
• /
• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.5
• /
• pp.43-51
• /
• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.2
• /
• pp.117-126
• /
• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.476-478
• /
• 2006

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a $0.25{\mu}m$ CMOS process. In the design a new dynamic D-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates up to 2.5GHz and consumes 3.1mA at 2.5GHz operation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.175-180
• /
• 2003

In this paper, we present a new method for early depth test for a 3D rendering engine. We add a filter stage to the rasterizer in the 3D rendering engine, in an attempt to identify and avoid the occluded pixels. This filtering block determines if a pixel is hidden by a certain plane. If a pixel is hidden by the plane, it can be removed. The simulation results show that the filter reduces the number of pixels to the next stage up to 71.7%. As a result, 67% of memory bandwidth is saved with simple extra hardware.

• Proceedings of the KIEE Conference
• /
• 2002.04a
• /
• pp.116-118
• /
• 2002

Of all known power quality problems, voltage sags provide the largest reason for concern. Sags occurs more frequently than outages and therefore tend to be more costly for industry as modern technical equipment becomes all the more sensitive to the quality and reliability of supply. Therefore we designed for a new model for Voltage Sag compensator, and we will implement Anti-Windup PI Controller with IP Block.