• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1281-1284
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• 2002

본 논문은 인터넷을 이용한 음성통신 서비스를 제공하기 위해 사용되는 VoIP 시스템 칩 설계 및 기능 검증을 위한 보드 개발에 관한 것이다. 구성이 간단한 시스템을 구현하기 위하여 32 비트 RISC 프로세서인 ARM922T 프로세서 코어를 중심으로 IP 망 접속 기능, 톤 발생 및 음성신호 접속기능과 다양한 사용자 정합 기능을 가지는 VoIP 시스템 칩을 설계하고, 이 칩의 기능을 검증하기 위하여 시험 프로그램 및 통신 프로토콜을 개발하였으며, 각종 설계 및 시뮬레이션 툴을 사용하고 ARM922T와 FPGA가 결합된 Excalibur를 사용한 시험용 보드를 개발하여 시험하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.1
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• pp.7-17
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• 2010

ITS(Intelligent Transport System) as things are used for Broadcast service using TDMB/TPEG/NAVI rather than personal seamless service. It is attaching weight to Traffic information gathering, Charging, Settlement service. This research is applied to improve DCCP(Datagram Congestion Control Protocol) which has function as protecting data and preserving message boundary. The improving method is like that we solve data trust in UDP because Connection and Transmission overhead in UDP is less than in TCP. We fix the data loss which is generated from unordered delivery section of IP base wireless service by using DCCP protocol. We guarantee of connection with OBE(On-Board Equipment) and reliance about transmission of data by complement to mapping table and multi-hoping. Finally, We evaluate the performance about transmission of IP based data. We constructed a test-bed near research center for this test.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.10a
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• pp.498-501
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• 2004

본 논문에서는 엘리베이터의 제어 신호들과 액추에이터들을 동작시키기 위한 릴레이 그리고 액츄에이터의 동작을 센서와 포토 커플러를 이용하여 샘플링 한다. 제안하는 시스템에서는 예외적인 상황에서 오류가 발생하는 사례를 퍼지 데이터베이스로 구성하고 산출된 엘리베이터에러를 최종적으로 엘리베이터 관리자에게 통보함으로써 사고 발생 시 즉각적인 대책과 인명피해에 대한 빠른 구조 활동을 계획할 수 있도록 한다. 시스템에 사용된 알고리즘은 제어 신호를 입력으로 한 퍼지 if-then rule 이며, 관리자와의 통신은 Bluetooth를 통하여 Embedded Server에 신호를 전송하고 최종적으로 Embedded Server에서 인터넷 IP를 통하여 관리자에게 에러 발생 여부를 통보하게 된다. 인터넷 IP를 활용함으로써 거리의 제약이 사라지고 실시간으로 엘리베이터의 상태를 파악 할 수 있게 된다. 궁극적으로 승객의 안전과 편의를 도모하기 위해 본 논문의 시스템이 제안되었다.

• Journal of information and communication convergence engineering
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• v.1 no.1
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• pp.48-52
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• 2003

A cost efficient IPSec Accelerator board utilizing a crypto chip and an entry-level Linux PC for the high performance VPN is presented in this paper. The IPIP (IP-over-IP tunneling) processing, encryption & decryption processing, HASH processing, and the integrity test functions of IPSec are processed in the IPSec Accelerator board. The proposed IPSec Accelerator has demonstrated successful execution of the required functions of the IPSec packet processing and verified its performance by processing the IPSec packets at the rate of over 1 Gbps.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.378-380
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• 2007

대화면 LCD TV (40인치 이상 LCD TV)에서 LCD 인버터의 가격 경쟁력을 위해 인버터 하나로 다수의 램프를 병렬 구동하면서 Two Stage System 구조인 Super IP Board 형태의 인버터 회로가 많이 사용되고 있다. 본 논문에서는 기존 Super IP Board의 인버터 구동 방식인 PWM 제어 방식을 분석하고, 문제점으로 제기되었던 Half-Bridge단 스위치의 하드 스위칭과 과도한 Circulating Energy 등의 문제를 해결한 새로운 Pulse Count Modulation (PCM) 방식을 적용한 인버터를 제안하고 이론적 및 실험적 검증을 통해 제안된 방식의 우수성을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.27-33
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• 2000

Nowadays is the increasing percentage of the aged in the population. Advanced age shows concern at own health status. So it is needed the home medical instrument which is cheap and connectable to hospital with a LAN or a public network In this paper, We have implemented a ECG (Electrocadiogram) terminal. The ECG terminal is composed of two parts. One is the analog board to remove the baseline drift. The other is the digital board consists of a data aquisition part and data transmission part. The ECG terminal doesn't have the display region to show a ECG curve and uses the modified digital filter to remove the power noise. The ECG terminal transmits a ECG signal with a LAM using TCP/IP. So ECG signal can be seen by the Central Patient Monitor Program connected TCP/IP network.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.307-310
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• 2001

A parameterized complex-number multiplier (PCMUL) core IP (Intellectual Property), which can be used as an essential arithmetic unit in baseband signal processing of digital communication systems, is described. The bit-width of the multiplier is parameterized in the range of 8-b~24-b and is user-selectable in 2-b step. The PCMUL_GEN, a core generator with GUI, generates VHDL code of a CMUL core for a specified bit-width. The IP is based on redundant binary (RB) arithmetic and a new radix4 Booth encoding/decoding scheme proposed in this paper. It results in a simplified internal structure, as well as high-speed, low-power, and area-efficient implementation. The designed IP was verified using Xilinx FPGA board.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.5
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• pp.434-437
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• 2002

A small size and light-weight DSP board is newly designed for a real time multi-distributed control system that overcomes constraints on time and space. There are a variety of protocols for a real-time distributed control system. In this research, we selected CAN for the multi distributed control, which was developed by the BOSCH in the early 1980's. If CAN and Internet are connected together, the system attains the characteristics of a distributed control system and a remote control system simultaneously. To build such a system. The TCP/IP-CAN Gateway which converts a CAN protocol to TCP/IP protocol and vice verse, was designed. Moreover, the system is required to be small and light-weighted for the high mobility and cost effectiveness. The equipment in remote place has a TCP/IP-CAN Gateway on itself to be able to communicate with another systems. The received commands in the remote site are converted from TCP/IP protocol to CAN protocol by the TCP/IP-CAN Gateway in real time. A simulation system consists of a TCP/IP-CAN Gateway in remote place and a command PC to be connected to Ethernet.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2462-2472
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• 2014

Recently, the computing paradigm has been changing and VoIP technology is being revisited to support various services. In this paper, we have designed and implemented the system of software PBX open source Asterisk, hardware platform, and mobile devices to support secured voice service based on VoIP. Specially, we designed the various platform from single board to servers based on XenServer in hardware platform. And we verified the delay test of network traffics and the secured voice communication test based on this platform.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.