• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.60-67
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• 2013

Test cost reduction is necessary to test a complex System-on-a-Chip(SoC) which adopts various Intellectual Properties (IP). In this paper, test architecture with low pin count which is able to IP-based SoC test, using IEEE Std. 1149.7 and IEEE Std. 1500, is proposed. IEEE Std. 1500 provides independent access mechanism for each IP in IP-based SoC test. In this paper, just two test pins are required by composing that these independent access mechanism can be controlled by IEEE Std. 1149.7. The number of Chips which are tested at the same time is increased by reducing required test pin count at wafer and package level test, and consequently the overall manufacturing test cost will be reduced significantly.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.465-472
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• 2016

This study materialized an FPGA-based system to extract PCB patterns. The Printed Circuit Boards that are produced these days are becoming more detailed and complex. Therefore, the importance of a vision system to extract defects of detailed patterns is increasing. This study produced an FPGA-based system that has high speed handling for vision automation of the PCB production process. A vision library that is used to extract defect patterns was also materialized in IPs to optimize the system. The IPs materialized are Camera Link IP, pattern matching IP, VGA IP, edge extraction IP, and memory IP.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.769-770
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• 2011

This paper presented a method constructing the ITSoC(Information Technology System-on-Chip). In order to implement the ITSoC, designers are increasing relying on reuse of intellectual property(IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. Also, embedded core in an ITSoC access mechanisms are required to test them at the system level. That is the goal, in theory. In practice, assembling an ITSoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discuss the main challenge in ITSoC designs using IP blocks and elaborates on the methodology and tools being put in place for addressing the problem. It explains ITSoC architecture and gives algorithmic details on the high-level tools being developed for ITSoC design.

• Journal of Korea Technology Innovation Society
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• v.12 no.2
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• pp.291-311
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• 2009

Intellectual Property(IP) investment and its management are an key driver to create corporate value and intangible asset value through corporate's competitiveness. The purposes of this study are to survey capability of IP management and assess the effects of IP investment and its management on the separation into groups of intangible asset value. In order to attain those purposes of this study, sample companies were taken and categorized into three groups by the level of intangible asset value ratio, and data for IP investment such as R&D expenditure and advertising expenditure were collected from 90 manufacturing companies, and data for IP management capability about patent, design and brand were taken through survey. The final results showed as followed: First, IP management capability were generally not sufficient in the results of survey. Second, mean vector for the four variables were significantly different among three groups in multivariate analysis variance. Third, the order of their contribution to separating the groups were R&D expenditure, advertising expenditure, patent management, management of design and brand in canonical variate analysis. Fourth, R&D and patent management capability were significantly related to the separation of three groups, while advertising expenditure were not significant and management of design and brand were not sure of Significance in multinomial logit discriminant analysis. Fifth, exploratory power of the discriminant model were estimated by 53% in classification analysis. Finally, strategic policy for IP investment and its management should be taken urgently to create intangible asset value and to improve the capability of its management.

• Journal of Digital Convergence
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• v.18 no.2
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• pp.421-426
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• 2020

The global game market is growing evenly across a variety of platforms, but in the Korean game market is a decline in growth rates on PC and mobile platforms, which account for more than 80% of the total Korean game market, which requires an alternative. In this study, propose a multi-platform launch of IP-based games as a way to increase the growth rate of the Korean game market. It has been analyzed that multi-platform launch methods can be divided into Stand-alone Multi-platform method, Interlocking multi-platform method, and Upgrade-interlinking Multi-platform method, respectively, and the effect of expanding, providing more satisfactory game play environment and preventing them from escaping to competitive games. Given the limited case analysis in this study, further studies are needed to propose more effective multi-platform utilization measures.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2002.11a
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• pp.63-68
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• 2002

JPEG2000은 기존의 정지영상압축부호화 방식에 비해 우수한 비트율-왜곡(Rate-Distortion)특성과 향상된 주관적 화질을 제공하며 인터넷, 디지털 영상카메라, 이동단말기, 의학영상 등 다양한 분야에서 적용될 수 있는 새로운 정지영상압축 표준이다. 본 논문에서는 SoC(System on a Chip)설계를 고려한 JPEG2000 인코더의 구조를 제안하고 IP(Intellectual Property)를 설계 및 검증하였다. 구현된 JPEG2000 IP는 DWT(Discrete Wavelet Transform)블록, 스칼라양자화블록, EBCOT(Embedded Block Coding with Optimized Truncation)블록으로 구성되어 있다. IP는 모의실험을 통해 구현 구조에 대한 타당성을 검증하였고, 반도체설계자산연구센터에서 제시한 'RTL Coding Guideline'에 따라 HDL을 설계하였다. 특히, DWT블록은 구현시 많은 연산과 메모리 용량이 필요하므로 영상을 저장할 외부 메모리를 사용하였고, 빠른 곱셈과 덧셈연산을 위한 3단 파이프라인 부스곱셈기(3-state pipeline booth multiplier)와 캐리예측 덧셈기(carry lookahead adder)를 사용하였다. 설계된 JPEG2000 IP들은 삼성 0.35$\mu\textrm{m}$ 라이브러리를 이용하여 Synopsys사 Design Analyzer 틀을 통해 논리 합성하였으며, Xillinx 100만 게이트 FPGA칩에 구현하여 그 동작을 검증하였다. 또한, Hard IP 설계를 위해 Avanti사의 Apollo툴을 이용하여 Layout을 수행하였다.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.509-518
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• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.597-600
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• 2004

In this paper. the soft IP (Intellectual Property) of pipeline of 32-bit microcontroller for embedded and portable application is presented. This IP supports variable pipeline stage according to the performance that user wants. In this architecture, three pipeline stages are basically employed and extended to the five pipeline stages. To this purpose, control logic has been partitioned to reflect each pipeline stage. FPGA platform is used for rapidly prototyping the IP. This is designed using Verilog HDL

• IT SoC Magazine
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• s.2
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• pp.34-38
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• 2004

실리콘 처리 기술의 고속화 요구와 유무선 환경에서 동영상 통신이 가능한 비디오 폰, 영상 회의 시스템, 이동 통신용 단말기 등의 전자 제품 사용자의 급증은 시스템을 하나의 칩에 집적화하는 SoC(System-On-a-Chip) 설계 기술을 요구하고 있다. 칩의 복잡도와 SoC 제품의 생산성 차이가 계속적으로 증가함에 따라 현재의 IC 설계 방법으로는 SoC 제품의 성능과 요구의 변화를 만족시킬 수 없다. 칩의 면적을 최소화하고 성능을 최대화하며 게이트 수준의 최적화를 통한 기존의 셀 기반 설계 방법으로는 설계의 생산성 문제를 해결할 수 없다. 이러한 문제를 해결 위한 새로운 설계 방법인 IP 재사용을 기반으로 한 플랫폼 기반 설계가 제시되었다. 플랫폼 기반 설계는 SoC 제품을 빠르게 개발하기 위한 응용 기반 통합 플랫폼과 재사용이 가능한 IP(Intellectual Property) 이용한 플랫폼 기반 설계(Platform-Based Design) 방법이다. 새로운 설계 방법은 90% 이상의 IP 재사용을 통해서 설계 시간을 단축하며, 시스템 수준에서의 최적화를 통해서 제품의 시장 경쟁력(Time-to-Market)의 문제를 해결하기 위한 방법이다.