• Journal of Institute of Control, Robotics and Systems
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• v.21 no.4
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• pp.378-384
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• 2015

Indoor localization is becoming one of the most important technologies for smart mobile applications with different requirements from conventional outdoor location estimation algorithms. Fingerprinting location estimation techniques based on neural networks have gained increasing attention from academia due to their good generalization properties. In this paper, we propose a novel location estimation algorithm based on an ensemble of multiple neural networks. The neural network ensemble has drawn much attention in various areas where one neural network fails to resolve and classify the given data due to its' inaccuracy, incompleteness, and ambiguity. To the best of our knowledge, this work is the first to enhance the location estimation accuracy in indoor wireless environments based on a neural network ensemble using fingerprinting training data. To evaluate the effectiveness of our proposed location estimation method, we conduct the numerical experiments using the TGn channel model that was developed by the 802.11n task group for evaluating high capacity WLAN technologies in indoor environments with multiple transmit and multiple receive antennas. The numerical results show that the proposed method based on the NNE technique outperforms the conventional methods and achieves very accurate estimation results even in environments with a low number of APs.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.7
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• pp.2972-2991
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• 2016

WLAN is the best choice in the place where complex network is hard to set up. Intelligent terminals are more and more assembled in some areas now. However, according to IEEE 802.11n/802.11ac, the access-point (AP) can only serve one user at a single frequency channel. The spectrum efficiency urgently needs to be improved. In theory, AP with multi-antenna can serve multiple users if these users do not interfere with each other. In this paper, we propose a user clustering scheme that could achieve multi-user selection through the mutual cooperation among users. We focus on two points, one is to achieve multi-user communication with multiple antennas technique at a single frequency channel, and the other one is to use a way of distributed users' collaboration to determine the multi-user selection for user clustering. Firstly, we use the CSMA/CA protocol to select the first user, and then we set this user as a source node using users' cooperation to search other proper users. With the help of the users' broadcast cooperation, we can search and select other appropriate user (while the number of access users is limited by the number of antennas in AP) to access AP with the first user simultaneously. In the network node searching, we propose a maximum degree energy routing searching algorithm, which uses the shortest time and traverses as many users as possible. We carried out the necessary analysis and simulation to prove the feasibility of the scheme. We hope this work may provide a new idea for the solution of the multiple access problem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.328-335
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• 2010

In this paper, an efficient algorithm and area-efficient hardware architecture have been proposed for $2{\times}2$ MIMO-OFDM based WLAN baseband modem with two transmit and two receive antennas. To enhance the performance of the receiver, the efficient timing synchronization algorithm and symbol detector based on MML algorithm are presented. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate, the complexity of the proposed architecture is dramatically decreased. The proposed area-efficient hardware design was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. As a result, the complexity of the proposed modem receiver is reduced by 56% over the conventional architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.726-732
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• 2019

In this study, we proposed an asymmetric differential inductor to improve the linearity of differential power amplifiers. Considering the phase error between differential signals of the differential amplifier, the location of the center tap of the differential inductor was modified to minimize the error. As a result, the center tap was positioned asymmetrically inside the differential inductor. With the asymmetric differential inductor, the AM-to-AM and AM-to-PM distortions of the amplifier were suppressed. To confirm the feasibility of the inductor, we designed a 2.4 GHz differential CMOS PA for IEEE 802.11n WLAN applications with a 64-quadrature amplitude modulation (QAM), 9.6 dB peak-to-average power ratio (PAPR), and a bandwidth of 20 MHz. The designed power amplifier was fabricated using the 180-nm RF CMOS process. The measured maximum linear output power was 17 dBm, whereas EVM was 5%.