• Title/Summary/Keyword: IEEE 802.11.ac/ad

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Implementation of Adaptive MCS in The IEEE 802.11ac/ad Wireless LAN (IEEE 802.11ac/ad 무선 LAN의 적응형 MCS 구현 연구)

  • Lee, Ha-cheol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.8
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    • pp.1613-1621
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    • 2015
  • This paper analyzes the rate adaptation scheme and suggests applicable strategy of the MCS(Modulation and Coding Scheme) for improving DCF throughput in the IEEE 802.11ad and 802.11ad wireless LAN. IEEE 802.11ac and 802.11ad wireless LAN provide MCS technique that dynamically adjusts modulation level and code rate to the time-varying channel conditions in order to obtain considerably high data rates. But these standards did not provide rate adaptation algorithm, so this paper surveyes rate adaptation algorithm and suggests MCS scheme applied to IEEE 802.11ac and 802.11ad wireless LAN. Specially A MAC(Medium Access Control) layer throughput is evaluated over error-prone channel in the IEEE 802.11ac-based wireless LAN. In this evaluation, DCF (Distributed Coordination Function) protocol and A-MPDU (MAC Protocol Data Unit Aggregation) scheme are used. Using theoretical analysis method, the MAC saturation throughput is evaluated with the PER (Packet Error Rate) on the condition that the number of station, transmission probability, the number of parallel beams and the number of frames in each A-MPDU are variables.

5세대 무선 LAN 기술 연구

  • Kwon, Oh-Hun;Kim, Yeo-Gyeom;Lee, Myoung-Hun;Kim, Hak-Beom
    • Review of KIISC
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    • v.22 no.5
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    • pp.79-89
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    • 2012
  • 최근 스마트폰 2000만 시대가 열리면서 무선 데이터 트래픽이 폭증하고 있다. 이동통신사들은 LTE 구축과 함께 네트워크 가상화 기술도입에 나섰고 기업들 역시 한 단계 진화된 무선 LAN 도입을 서두르고 있다. 이러한 무선 LAN을 이용한 스마트폰 수요 및 태블릿 PC 가 폭발적으로 증가함에 따라 무선 LAN에 기반한 새로운 기술들이 활발히 논의되고 있다. 현재 사용자들이 가장 많이 사용하고 있는 802.11n의 후속으로, 차세대 스마트폰을 위한 핵심 기술로서 고용량 데이터 및 동영상을 보낼 수 있는 Gbps급 전송을 지원하는 IEEE 802.11 ac, IEEE 802.11 ad가 연구 중이다. 또한 광역 서비스를 지원하는 IEEE 802.11 af 및 IEEE 802.11 ah, 인증서비스를 간소화하여 초기링크 셋업시간을 감소시켜주는 IEEE 802.11 ai에 대해 본 논문에서는 무선 LAN 그룹의 연구와 분석에 대해 기술하고자 한다.

Technologies trend for Wireless LAN (무선 LAN 통신망의 기술 동향)

  • Gang, Yeong-Jin;Kim, Sung-Nam;Kang, Sin-Ill;Lee, Yeong-Sil;Lee, Hoon-Jae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.10a
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    • pp.255-258
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    • 2011
  • Wi-Fi is a rapidly spreading communications network with Smart phone's publication, the technology has become Ubiquitous-based core network which is connected to personal computers, laptops, and tablet PC. Wi-Fi can send currently a variety of data standard due to developed wireless LAN communications network. One of Wi-Fi standard protocols, which is IEEE 802.11n, use 2.4GHz and 5GHz band. 2.4GHz band is used for 802.11b/g protocol because wavelength is long, diffraction and receiving distance is enough to connect other device. 5GHz band has more available channels to use than 2.4GHz band, so there is no frequency interference of other wireless device such as Bluetooth, RFID. Moreover, there is low interference between channels due to small users in each bandwidth level. In the thesis, we are going to analyze 802.11a/b/g protocol which has used since the beginning of Wi-Fi protocol and 802.11n protocol which is used lately. Furthermore, we look into development and direction for standardization of the next generation wireless LANs which are 802.11ac and 802.11ad. In addition, we will consider for the security, vulnerabilities and its countermeasure in Wireless LAN.

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차세대 WLAN 시스템의 기술 개발 및 시장 동향

  • Park, Sang-Hun;Lee, Han-Rim;Kim, Gi-Jin;Im, Tae-Ho;An, Gwang-Ho
    • Information and Communications Magazine
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    • v.28 no.11
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    • pp.56-65
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    • 2011
  • 가정, 기업, 오피스 및 공공장소에서의 폭넓은 무선 데이터 서비스 사용에 따라 거대한 영향력과 시장성을 갖게 될 차세대 WLAN 기술 및 시스템에 대한 관심이 더욱 높아지고 있다. 본고에서는 IEEE 802.11의 표준 기술 및 표준화 진행 중인 개발 기술들에 대해 살펴본다. WLAN을 기반으로 하는 IEEE 802.11의 간략한 history와 배경뿐만 아니라, IEEE 802.11a/b/g/n/ac/ad 등의 기술적인 부분을 요약하여 개발 현황을 알아보고, 확보된 기술을 통한 시장 상태와 차세대 기술개발을 통한 시장동향을 논의한다.

Efficient Scheduling Schemes for Low-Area Mixed-radix MDC FFT Processor (저면적 Mixed-radix MDC FFT 프로세서를 위한 효율적인 스케줄링 기법)

  • Jang, Jeong Keun;Sunwoo, Myung Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.7
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    • pp.29-35
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    • 2017
  • This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

New Parallel MDC FFT Processor for Low Computation Complexity (연산복잡도 감소를 위한 새로운 8-병렬 MDC FFT 프로세서)

  • Kim, Moon Gi;Sunwoo, Myung Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.3
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    • pp.75-81
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    • 2015
  • This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.