• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3A
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• pp.399-405
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• 2000

In this paper, we deal with block cipher algorithm IDEA(international data encryption algorithm), previously known as typical block cipher system. first of all, analysing key scheduler we classify the key sequences with the used key bit and the unused key bits in each round. with this properties we propose the two method, which are differential analysis using differences of plaintext pairs and linear analysis using LSB bit of plaintexts and key sequences.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.855-858
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• 1999

In this paper, we present a FPCA implementation of IDEA algorithm. Target technology is Altera FLEX 10K FPCA. The correctness of the implementation is verified by the timing simulation with max+plus II.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.69-74
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• 1999

This paper describes the principles of IDEA(international data encryption algorithm) which has been widely accepted as a data encryption algorithm and the implementation of the algorithm on the TMS320C54X DSP board is addressed. It is also shown that the processing time is significantly reduced by adapting high speed multiplication modulo (2^16+1) algorithm. The result shows data rates of about 250∼300Mbyte/sec.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.6
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• pp.696-702
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• 2001

In this paper, we design IDEA cipher algorithm which is cryptographically superior to DES. To improve the encryption throughput, we propose an efficient design methodology for high-speed implementation of multiplicative inverse modulo $2^{15}$+1 which requires the most computing powers in IDEA. The efficient hardware architecture for the multiplicative inverse in derived from applying of Fermat's Theorem. The computing powers for multiplicative inverse in our proposal is a decrease 50% compared with the existing method based on Extended Euclid Algorithm. We implement IDEA by applying a single iterative round method and our proposal for multiplicative inverse. With a system clock frequency 20MGz, the designed hardware permits a data conversion rate of more than 116 Mbit/s. This result show that the designed device operates about 2 times than the result of the paper by H. Bonnenberg et al. From a speed point of view, out proposal for multiplicative inverse is proved to be efficient.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.377-382
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• 1998

본 논문에서는 암호화 알고리즘인 IDEA(International Data Encryption Algorithm)를 분석하고 TMS320C542 EVM 보드에서 어셈블리 언어로 구현하였다. 또한 수행 속도에 매우 큰 영향을 미치는 핵심 연산인 모듈러 곱셈 연산에 대한 고속 알고리즘을 채택하여 속도 개선을 이루었다.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10b
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• pp.13-17
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• 1993

In this paper, a design method of controller which incorporates pole restriction into implicit self tuning algorithm is proposed. The idea behind pole restriction is that the closed loop poles of the system are restricted to a user-chosen circle in the region to meet maximum percentage overshoot and settling time specification. Most algorithm based on pole restriction are explicit schemes involving a parameter estimation and synthesis stage to obtain controller parameters. The object of this paper is to have an algorithm that has the idea of pole restriction and the simplicity of the implicit approach.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.2
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• pp.81-94
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• 2012

This paper suggests PARED algorithm, a modified RED algorithm, that actively reacts to dynamic changes in network to apply packet drop probability flexibly. The main idea of PARED algorithm is that it compares the target queue length to the average queue length which is the criterion of changes in packet drop probability and feeds the gap into packet drop probability. That is, when the difference between the average queue length and the target queue length is great, it reflects as much as the difference in packet drop probability, and reflects little when the difference is little. By doing so, packet drop probability could be actively controled and effectively dealt with in the network traffic situation. To evaluate the performance of the suggested algorithm, we conducted simulations by changing network traffic into a dynamic stat. At the experiments, the suggested algorithm was compared to the existing RED one and then to ARED one that provided the basic idea for this algorithm. The results proved that the suggested PARED algorithm is superior to the existing algorithms.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1998.12a
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• pp.483-493
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• 1998

본 논문에서 DES를 대체하기 위해 몇 년에 걸쳐 제안된 관용 암호알고리즘의 하나인 IDEA(International Data Encryption Algorithm)의 구현을 제안하고자 한다. IDEA의 암호화 수행시간의 개선을 위하여 VHDL(VHSIC Hardware Description Language)을 이용하여 하드웨어로 설계하였고 설계된 알고리즘은 EDA tool인 Synopsys를 사용하여 Synthesis하였으며, Xilinx의 FPGA XC4052XL을 이용하여 One Chip화 시켰다. 입력 클럭으로 30MHz를 사용하였을 때, data arrival time은 780.09ns였으며, 80.01 Mbps의 속도로 동작하였다. 본 논문은 설계 언어로서 VHDL을 사용하였고, FPGA Chip에 구현하여 동작 확인을 하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.347-350
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• 1998

최근 개인 휴대통신과 컴퓨터 기술의 발달로 유용한 데이터의 질적.양적 향상을 가져왔다. 이로 인해 저장중이거나 선로상에서의 전송중인 정보의 보호문제가 중요시되고 있다. 이러한 정보보호 문제가 중요시됨에 따라 정보보호를 위한 직접적인 암호화 방법중의 하나인 IDEA(International Data Encryption Algorithm)의 구현을 제안하고자 한다. IDEA는 블록 암호화 방식의 하나로서 64비트 데이터를 암호화하기 위해 128비트의 키를 사용한다. 본 논문에서 암호알고리즘 구현을 위하여 하드웨어 설계언어인 VHDL을 사용하였고, V-System을 이용하여 Simulation을 수행하였다. Coding된 알고리즘은 Synopsy를 사용하여 자동합성하였고, Xilinx사의 FPGA-4025를 Target으로 구현하였다.