• 한국항공우주학회지
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• 제41권1호
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• pp.79-84
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• 2013

DC/DC 컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 효율이 높은 전력변환기이다. DC/DC 컨버터는 PWM-IC(펄스폭 변조 집적회로) 제어기, MOSFET(산화물-반도체 전계 효과 트랜지스터), 인덕터, 콘덴서 등으로 구성되어있다. 코발트 60 ($^{60}Co$) 저준위 감마발생기를 이용한 TID실험에서 방사선의 영향으로 PWM-IC의 전기적 특성중에 문턱전압과 옵셋전압이 증가되고, SEL에 적용된 4종류의 중이온 입자는 PWM-IC의 파형을 불안정하게 만든다. 또한, 입/출력관계의 파형을 SPICE 시뮬레이션 프로그램으로 관찰하였다. PWM-IC의 TID 실험은 30 Krad 까지 수행하였으며, SEL 실험을 제어보드를 구현한 후 LET($MeV/mg/cm^2$)별 cross section($cm^2$)으로 연구하였다.

• 비파괴검사학회지
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• 제12권4호
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• pp.18-25
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• 1993

This paper is to aim the microdefect evaluation of If package into a quantitative from NDI's image processing of ultrasonic wave. (1) Automatically repeated discrimination analysis method can be devided in the category of all kind of defects on IC package, and also can be possible to have a sampling of partial delamination. (2) It is possible that the information of edge section in silicon chip surrounding can be extractor by the partial image processing of IC package. Also, the crack detection is possible between the resin part and lead frame.

• International Journal of Quality Innovation
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• 제8권3호
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• pp.81-112
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• 2007

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five-point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1005-1008
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• 1998

IC testing plays a very important role in IC manufacturing process. Modern complex ASIC chips making it difficult for gate level and RLT level test generation techniques to generate good test vector in resonable time. In this paper we proposed new test pattern generation method in VHDL description to detect manufacturing faults. This method based on software testing can easily generate test vector and independent to synthesis result.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.107-110
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• 2002

Soft masks mean that part or all of the program code for operating system or applications are located in the EEPROM or flash ROM. Since Soft masks allow errors to be corrected and programs to be modified quickly and at minimal cost, they are used primarily during testing and in the field trials. This paper introduces a hardware architecture of IC card for soft masks. We suggest a new down loading scheme for soft-mask ROM connected by an I/O interface. This scheme saves the new IC card development cost and time.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• 전자공학회논문지
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• 제50권1호
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• pp.131-136
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• 2013

칩 적층기술의 발달로 TSV(Through Silicon Via) 기반 3D IC가 개발되었다. 3D IC의 높은 신뢰성과 수율을 얻기 위해서는 pre-bond 와 post-bond 수준에서 다양한 TSV 테스트가 필수적이다. 본 논문에서는 pre-bond 다이의 TSV 연결부에서 발생하는 미세한 고장과 post-bond 적층된 3D IC의 TSV 연결선에서 발생하는 다양한 고장을 테스트할 수 있는 설계기술을 소개한다. IEEE 1500 표준 기반의 래퍼셀을 보완하여 TSV 기반 3D IC pre-bond 및 post-bond의 at speed test를 통하여 known-good-die와 무결점의 3D IC를 제작하고자 한다.

• 한국방사선학회논문지
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• 제11권3호
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• pp.101-108
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• 2017

DC/DC 컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 효율이 높은 전력변환기이다. 고급형 DC/DC 컨버터는 MOSFET(산화물-반도체 전계 효과 트랜지스터)를 제어하기 위해 OP-Amp.(연산 증폭기)를 실장한 PWM-IC(펄스폭 변조 집적회로)를 사용한다. OP-Amp.는 증폭기 기능을 수행하는데 방사선 영향으로 전기적 특성이 변화하는데 본 논문에서는 코발트 60 (60Co) 저준위 감마발생기를 이용한 TID실험과 5종류의 중이온 입자를 이용하여 SEL 실험을 수행하는데 바이어스(bias) 전류가 순간적으로 과전류가 흘러 SEL이 발생된다. OP-Amp.의 TID 실험은 조사율은 5 rad/sec.로 전체 조사량을 30 krad 까지 수행하였으며, SEL 실험은 제어보드를 구현한 후 LET($MeV/mg/cm^2$)별 cross section($cm^2$)을 이용하여 성능평가를 하는데 있다.

• The Journal of Advanced Prosthodontics
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• 제5권1호
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• pp.36-43
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• 2013

PURPOSE. The objective of this study was to compare the fracture toughness ($K_{Ic}$) obtained from the single edge V-notched beam (SEVNB) and the fractographic analysis (FTA) of a glass-infiltrated and a zirconia ceramic. MATERIALS AND METHODS. For each material, ten bar-shaped specimens were prepared for the SEVNB method ($3mm{\times}4mm{\times}25mm$) and the FTA method ($2mm{\times}4mm{\times}25mm$). The starter V-notch was prepared as the fracture initiating flaw for the SEVNB method. A Vickers indentation load of 49 N was used to create a controlled surface flaw on each FTA specimen. All specimens were loaded to fracture using a universal testing machine at a crosshead speed of 0.5-1 mm/min. The independent-samples t-test was used for the statistical analysis of the $K_{Ic}$ values at ${\alpha}$=0.05. RESULTS. The mean $K_{Ic}$ of zirconia ceramic obtained from SEVNB method ($5.4{\pm}1.6\;MPa{\cdot}m^{1/2}$) was comparable to that obtained from FTA method ($6.3{\pm}1.6\;MPa{\cdot}m^{1/2}$). The mean $K_{Ic}$ of glass-infiltrated ceramic obtained from SEVNB method ($4.1{\pm}0.6\;MPa{\cdot}m^{1/2}$) was significantly lower than that obtained from FTA method ($5.1{\pm}0.7\;MPa{\cdot}m^{1/2}$). CONCLUSION. The mean $K_{Ic}$ of the glass-infiltrated and zirconia ceramics obtained from the SEVNB method were lower than those obtained from FTA method even they were not significantly different for the zirconia material. The differences in the $K_{Ic}$ values could be a result of the differences in the characteristics of fracture initiating flaws of these two methods.