• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.41 no.1
• /
• pp.79-84
• /
• 2013

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a PWM-IC (pulse width modulation-integrated circuit) controller, a MOSFET (metal-oxide semiconductor field effect transistor), inductor, capacitor, etc. It is shown that the variation of threshold voltage and the offset voltage in the electrical characteristics of PWM-IC increase by radiation effects in TID (Total Ionizing Dose) testing at the low energy ${\gamma}$ rays using $^{60}Co$, and 4 heavy ions applied for SEL (Single Event Latch-up) make the PWM pulse unstable. Also, the output waveform for the given input in the DC/DC converter is observed by the simulation program with integrated circuit emphasis (SPICE). TID testing on PWM-IC is accomplished up to the total dose of 30 krad, and the cross section($cm^2$) versus LET($MeV/mg/cm^2$) in the PWM operation is studied at SEL testing after implementation of the controller board.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.12 no.4
• /
• pp.18-25
• /
• 1993

This paper is to aim the microdefect evaluation of If package into a quantitative from NDI's image processing of ultrasonic wave. (1) Automatically repeated discrimination analysis method can be devided in the category of all kind of defects on IC package, and also can be possible to have a sampling of partial delamination. (2) It is possible that the information of edge section in silicon chip surrounding can be extractor by the partial image processing of IC package. Also, the crack detection is possible between the resin part and lead frame.

• International Journal of Quality Innovation
• /
• v.8 no.3
• /
• pp.81-112
• /
• 2007

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five-point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1005-1008
• /
• 1998

IC testing plays a very important role in IC manufacturing process. Modern complex ASIC chips making it difficult for gate level and RLT level test generation techniques to generate good test vector in resonable time. In this paper we proposed new test pattern generation method in VHDL description to detect manufacturing faults. This method based on software testing can easily generate test vector and independent to synthesis result.

• Proceedings of the IEEK Conference
• /
• 2002.06e
• /
• pp.107-110
• /
• 2002

Soft masks mean that part or all of the program code for operating system or applications are located in the EEPROM or flash ROM. Since Soft masks allow errors to be corrected and programs to be modified quickly and at minimal cost, they are used primarily during testing and in the field trials. This paper introduces a hardware architecture of IC card for soft masks. We suggest a new down loading scheme for soft-mask ROM connected by an I/O interface. This scheme saves the new IC card development cost and time.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.792-793
• /
• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.5
• /
• pp.431-438
• /
• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.131-136
• /
• 2013

TSV based 3D ICs have been widely developed with new problems at die and IC levels. It is imperative to test at post-bond as well as pre-bond to achieve high reliability and yield. This paper introduces a new testable design technique which not only test microscopic defects at TSV input/output contact at a die but also test interconnect defects at a stacked IC. IEEE 1500 wrapper cells are augmented and through at-speed tests for pre-bond die and post-bond IC, known-good-die and defect free 3D IC can be massively manufactured+.

• Journal of the Korean Society of Radiology
• /
• v.11 no.3
• /
• pp.101-108
• /
• 2017

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The advanced DC/DC converter uses a PWM-IC with OP-Amp. (Operational Amplifier) to control a MOSFET (metal-oxide semiconductor field effect transistor), which is a switching component, efficiently. In this paper, it is shown that the electrical characteristics of OP-Amp. are affected by radiations of ${\gamma}$ rays using $^{60}Co$ for TID (Total Ionizing Dose) testing and 5 heavy ions for SEL (Single Event Latch-up) testing. TID testing on OP-Amp. is accomplished up to the total dose of 30 krad, and the cross section($cm^2$) versus LET($MeV/mg/cm^2$) in the OP-Amp. operation is evaluated SEL testing after implementation of the controller board.

• The Journal of Advanced Prosthodontics
• /
• v.5 no.1
• /
• pp.36-43
• /
• 2013

PURPOSE. The objective of this study was to compare the fracture toughness ($K_{Ic}$) obtained from the single edge V-notched beam (SEVNB) and the fractographic analysis (FTA) of a glass-infiltrated and a zirconia ceramic. MATERIALS AND METHODS. For each material, ten bar-shaped specimens were prepared for the SEVNB method ($3mm{\times}4mm{\times}25mm$) and the FTA method ($2mm{\times}4mm{\times}25mm$). The starter V-notch was prepared as the fracture initiating flaw for the SEVNB method. A Vickers indentation load of 49 N was used to create a controlled surface flaw on each FTA specimen. All specimens were loaded to fracture using a universal testing machine at a crosshead speed of 0.5-1 mm/min. The independent-samples t-test was used for the statistical analysis of the $K_{Ic}$ values at ${\alpha}$=0.05. RESULTS. The mean $K_{Ic}$ of zirconia ceramic obtained from SEVNB method ($5.4{\pm}1.6\;MPa{\cdot}m^{1/2}$) was comparable to that obtained from FTA method ($6.3{\pm}1.6\;MPa{\cdot}m^{1/2}$). The mean $K_{Ic}$ of glass-infiltrated ceramic obtained from SEVNB method ($4.1{\pm}0.6\;MPa{\cdot}m^{1/2}$) was significantly lower than that obtained from FTA method ($5.1{\pm}0.7\;MPa{\cdot}m^{1/2}$). CONCLUSION. The mean $K_{Ic}$ of the glass-infiltrated and zirconia ceramics obtained from the SEVNB method were lower than those obtained from FTA method even they were not significantly different for the zirconia material. The differences in the $K_{Ic}$ values could be a result of the differences in the characteristics of fracture initiating flaws of these two methods.