• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.527-527
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• 1996

• Proceedings of the Korean Magnestics Society Conference
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• 2003.06a
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• pp.44-45
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• 2003

• 한국초전도학회:학술대회논문집
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• 2007.07a
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• pp.36-36
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• 2007

• Bulletin of the Korean Chemical Society
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• v.30 no.11
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• pp.2785-2788
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• 2009

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.470-473
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased patting density. The devices are scaled down day by day. Therefore, This paper investigates how MOSFET structures influence on transport properties in according to change of channel length and bias and, observes impact ionization between the drain and the gate. This paper proposes three models, i.e., conventional MOSFET, LDD MOSFET and EPI MOSFET. The gate lengths are 0.3$\mu\textrm{m}$ 0.15$\mu\textrm{m}$, 0.075$\mu\textrm{m}$ and scaling factor is λ = 2. We have presented MOSFET's characteristics such as I-V characteristic, impart ionization, electric field, using the TCAD. We have analyzed the adaptive channel and doping influences

• Publications of The Korean Astronomical Society
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• v.22 no.4
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• pp.177-181
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• 2007

We present the sensitivity calculation results for observing the Cosmic Infrared Background (CIRB) by the Multi-purpose IR Imaging System (MIRIS), which will be launched in 2010 as a main payload of the Science and Technology Satellite 3 (STSAT-3). MIRIS will observe in I ($0.9{\sim}1.2um$) and H ($1.2{\sim}2.0um$) band with a $4{\times}4$ degree field of view to obtain the large scale structure (${\sim}3$ degree) of the CIRB. With the given specifications of the MIRIS, our sensitivity calculation results show that the MIRIS has a detection limit of ${\sim}9\;nW\;m^{-2}\;sr^{-1}$ (I band) and ${\sim}6\;nW\;m^{-2}\;sr^{-1}$ (H band), which is appropriate to observe the large scale structure of CIRB.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.10
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• pp.1982-1988
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• 2002

Micro-injection molding and microfluidic devices with the help of MEMS technologies including the LIGA process are expected to play important roles in micro-system industries, in particular the bio-application industry, in the near future. Understanding fluid flows in micro-channels is important since micro-channels are typical geometry in various microfluidic devices and mold inserts for micro-injection molding. In the present study, Part 1, an experimental investigation has been carried out to understand the detailed flow phenomena in micro-channel filling process. Three sets of micro-channels of different thickness (40um,30um and 2011m) were fabricated using SU-8 on silicon wafer substrate. And a flow visualization system was developed to observe the filling flow into the micro-channels. Experimental flow observations are extensively made to find the effects of pressure, inertia force, viscous force and surface tension. A dimensional analysis for experimental results was carried out and several relationships A dimensionless parameters are obtained.

• Journal of Biomedical Engineering Research
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• v.19 no.3
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• pp.225-232
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• 1998

Results of Monte Carlo simulations on amorphous silicon based x-ray imaging arrays are described. In order to investigate the characteristics of amorphous silicon x-ray imaging devices and to provide the optimum design parameter, Monte Carlo simulations were performed. Monte Carlo simulation codes for our purpose were developed and various combinations of x-ray peak voltages, aluminum filter thicknesses, CsI(TI) thicknesses, and amorphous silicon photodiode pixel sizes were tested in connection with detection efficiency and spatial resolution of the amorphous silicon based x-ray imager. With usual Csl(TI) thickness of 300${\mu}{\textrm}{m}$-500${\mu}{\textrm}{m}$, detection efficiency was in the range of 70%-95% and energy absorption efficiency was in the range of 40%-70% for 60kVp-120kVp x-ray. From the simulations it was found that amorphous silicon pixel size and Csl(TI) thickness were the most important parameters which determine the resolution of the imager. By use of our simulation results we could provide proper combinations of Csl(TI) thicknesses and pixels sizes for optimum sensitivity and resolution.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.