• 한국전기전자재료학회논문지
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• 제28권10호
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• pp.658-664
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• 2015

This paper presents an electrical feature analysis of hysteresis curves in memristor differential and intergral control circuit. After making macro model of the memristor device, electric characteristics of the model such as time analysis, frequency dependent DC I-V curves were performed by PSPICE simulation. Also, we made a circuit of memristor-capacitor based on nano-wired memristor device and analyzed the simulated PSPICE results. Finally, we proposed a memristor based differential or integral control circuit, analyzed hysteresis curve characteristic in the control circuit.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.172-173
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• 2006

Metal-ferroelectric-insulator-semiconductor (MFIS) structures with $Bi_{3.35}La_{0.75}Ti_3O_{12}$ (BLT) ferroelectric film and Zirconium oxide ($ZrO_2$) layer were fabricated on p-type Si(100). $ZrO_2$ and BLT films were prepared by sol-gel technique. Surface morphologies of $ZrO_2$ and BLT film were measured by atomic force microscope (AFM). The electrical characteristics of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si film were investigated by C-V and I-V measurements. No hysteretic characteristics was observed in the C-V curve of the Au/$ZrO_2$/Si structure. The memory window width m C-V curve of the Au/BLT/$ZrO_2$/Si diode was about 1.3 V for a voltage sweep of ${\pm}5$ V. The leakage current of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si structures were about $3{\times}10^{-8}$ A at 30 MV/cm and $3{\times}10^{-8}$ A at 3 MV/cm, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 추계학술대회 논문집
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• pp.136-140
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• 1992

The purpose of this research is to develop the lithium secondary battery. This paper describes the preparation, electrochemical properties of nontstoichiometric(NS)-$V_6O_{13}$ and characteristics of Li/$V_6O_{13}$ secondary battery. NS-$V_6O_{13}$ was prepared by thermal decomposition of $NH_4VO_3$ under Ar stream of 140ml/min~180ml/min flow rate. And then, this NS-$V_6O_{13}$ was used for cathode active material. Cathode sheet was prepared by compressing the composite of NS-$V_6O_{13}$, acetylene black(A.B) and teflon emulsion (T.E). Characteristics of the test cell are summarised as follows. Oxidation capacity of NS-$V_6O_{13}$ was about 20% less than its reduction capacity. A part of NS-$V_6O_{13}$ cathode active material showed irreversible reaction in early charge-discharge cycle. This phenomena seems to be caused by irreversible incoporation/discoporation of lithium cation to/from NS-$V_6O_{13}$ host. Discharge characteristics curve of Li/$V_6O_{13}$ cell showed 4 potential plateaus. Charge-discharge capacity was declined in the beginning of cycling and slowly increased in company with increasing of coulombic efficiency. Energy density per weight of $V_6O_{13}$ cathode material was as high as 522Wh/kg~765Wh/kg.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 추계종합학술대회
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• pp.665-668
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• 2001

최근 소자의 크기가 작아짐에 따라 집적도가 향상되었으며 크기 감소로 인한 전류-전압 특성의 열화 및 기생 커패시턴스에 의한 성능감쇠가 발생하였다. 이런 문제들을 해결하기 위해 여러 가지 구조들이 개발되고 있으며 본 논문에서는 고농도로 도핑된 ground plane 층위에 적층하여 만든 EPI 구조에 대해 조사 분석하였다. 이 구조의 특성과 임팩트 이온화 및 전계 그리고 I-V 특성 곡선을 저농도로 도핑된 LDD(Lightly Doped Drain) 구조와 비교 분석하였다. 소자의 채널 길이는 0.l0$\mu\textrm{m}$부터 0.06$\mu\textrm{m}$까지 0.01$\mu\textrm{m}$씩 스케일링하여 시뮬레이션 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.63-66
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• 1995

The ohmic characterization of Au/Te/Au/n-GaAs structure is investigated by the application of x-ray diffraction, scanning electron microscopy, Auger electron spectroscopy, the specific contact resistance and I-V measurement. Increasing the annealing temperature, the results of XRD measurement show the sharpening of the Au-Ga peak and the increasing of the intensity of Au peak due to the crystallization. At 400$^{\circ}C$, which is the ohmic onset point, Ga$_2$Te$_3$peak gets evident and GaAs regrowth peak appears for the samples annealed at 500$^{\circ}C$. The variation of shottky contact to ohmic contact is confirmed by the I-V curve transition. The specific contact resistance of 3.8x10$\^$-5/$\Omega$-$\textrm{cm}^2$ is obtained for the sample annealed at 500$^{\circ}C$ and above 600$^{\circ}C$ the specific contact resistance increased due to the decomposition of GaAs substrate.

• Journal of Multimedia Information System
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• 제8권2호
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• pp.143-146
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• 2021

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.

• 한국정보통신학회논문지
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• 제5권3호
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• pp.573-579
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• 2001

소자의 고집적을 위한 특성분석 기술은 빠른 변화를 보이고 있다. 이에 따라 고집적 소자의 특성을 시뮬레이션을 통하여 이해하고 이에 맞게 제작하는 기술은 매우 중요한 과제 중의 하나가 되었다. 소자가 마이크론급에서 나노급 이하로 작아지면서 그에 맞는 소자개발을 위해 여러 가지 구조가 제시되고 있는데 본 논문에서는 TCAD를 이용하여 여러 가지 구조 중에서 고농도로 도핑된 ground plane 위에 적층하여 만든 EPI MOSFET를 조사하였다. 이 구조의 특성과 임팩트이온화와 전계 그리고 I-V특성 곡선을 저 농도로 도핑된 드레인(LDD)MOSFET와 비교 분석하였다. 또한 TCAD의 유용성을 조사하여 시뮬레이터로서 적합함과 나노구조 소자에서의 스켈링이론의 적합함을 보았다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 춘계종합학술대회
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• pp.311-316
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• 2001

소자의 고집적을 위한 특성분석 기술은 빠른 변화를 보이고 있다. 이에 따라 고집적 소자의 특성을 시뮬레이션을 통하여 이해하고 이에 맞게 제작하는 기술을 매우 중요한 과제 중의 하나가 되었다. 소자가 마이크론급에서 나노급 이하로 작아지면서 그에 맞는 소자개발을 위해 여러 가지 구조가 제시되고 있는데 본 논문에서는 TCAD를 이용하여 여러 가지 구조 중에서 고농도로 도핑된 ground plane 위에 적층하여 만든 EFI MOSFET와 LDD구조의 단점을 개선한 newEPI MOSFET에 대해 조사하였다. 이 구조의 특성과 임팩트이온화와 전계 그리고 I-V 특성 곡선을 저 농도로 도핑된 드레인(LDD) MOSFET와 비교 분석하였다. 또한 TCAD의 유용성을 조사하여 시뮬레이터로서 적합함과 나노구조 소자에서의 스켈링이론의 적합함을 보았다.

• 한국안전학회지
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• 제9권1호
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• pp.56-60
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• 1994

In this study, Cuttent vs. Temperature characteristics of polyethylene with high-voltage treatment and crystallinity have been studied. The current curve( $I_{th}$) shows two peaks at 85 ($^{\circ}C$) and 50($^{\circ}C$), respectively. Trapping of carriers Proceeds during the high-field treatment, and it Is clear that 1th arises from the drift of carriers under the external voltage( $V_{b}$). From the results of TSC of BDPE and LDPE. It is realized that the traps are relation to the crystallinity.y.y.

• 대한전자공학회논문지
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• 제24권1호
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• pp.67-72
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• 1987

InSb TFT is fabricated by the vacuum evaporation method and I-V characteristics are measured. Employing Davidon Fletcher-Powell algorithm, the device parameters are extracted. The current-voltage relations calculated by extracdted parameters are in good agreement with experimental results. It is found that optimization technique may be more simple and accurate than curve fitting method in device parameters extration.