• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.163-166
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• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

• 한국통신학회논문지
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• 제27권3A호
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• pp.196-204
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• 2002

STC(Sinusoidal Transform Coding) 방식은 주파수 영역에서 음성신호의 스펙트럼 피크치들을 정현파로 모델링하여 합성하는 음성부호화 방식을 말한다. 저전송률 STC 방식에서는 스펙트럼의 모든 피크를 이용하는 대신, 기본 주파수와 고조파에 해당하는 스펙트럼 포락선에서의 크기와 그때의 위상을 이용하여 음성을 합성한다. 본 논문에서는 정현파 모델에 기반한 2.4kbps 음성부호화 알고리즘을 제안한다. 피치정보는 모든 스펙트럼 피크를 사용한 합성음과 선택된 주파수와 고조파를 이용한 합성음과의 평균자승에러를 이용하여 추정하고, 위상정보는 여기신호 펄스의 시작시기를 나타내는 onset time과 성도 모델 전달함수의 위상을 이용하여 얻는다. 크기정보는 SEEVOC 알고리즘과 선형예측계수를 이용하여 추정한다. 실험결과, 합성음의 스펙트럼 특성은 원음성의 포만트 정보를 대부분 가지고 있으며, 위상정보도 원음성의 위상을 잘 따라감을 확인하였다. 합성음의 음질평가를 위해서 informal한 MOS(Mean Opinion Score) 테스트를 시행하였으며, 2.0kbps의 HVXC와 비교하여 대체적으로 MOS 3.1 이상의 음질을 얻을 수 있었다.

• Bulletin of the Korean Chemical Society
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• 제21권7호
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• pp.720-726
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• 2000

The analytic gradient method for the equation-of-motion coupled-cluster singles and doubles (EOM-CCSD) energy has been extended to employ a reduced molecular orbital (MO) space. Not only the innermost core MOs but also some of the outermost virtua l MOs can be dropped in the reduced MO space, and a substantial amount of computation time can be reduced without deteriorating the results. In order to study the magnitudes and trends of the effects of the dropped MOs, the geometries and vibrational properties of the ground and excited states of BF, CO, CN, N2, AlCl, SiS, P2, BCl, AIF, CS, SiO, PN and GeSe are calculated with different sizes of molecular orbital space. The 6-31 G* and the aug-cc-pVTZ basis sets are employed for all molecules except GeSc for which the 6-311 G* and the TZV+f basis sets are used. It is shown that the magnitudes of the drop-MO effects are about $0.005\AA$ in bond lengths and about 1% on harmonic frequencies and IR intensities provided that the dropped MOs correspond to (1s), (1s,2s,2p), an (1s,2s,2p,3s,3p) atomic orbitals of the first, the second, and the third row atoms, respectively. The geometries and vibrational properties of the first and the second excited states of HCN and HNC are calculated by using a drastically reduced virtual MO space as well as with the well defined frozen core MO space. The results suggest the possibility of using a very smalI MO space for qualitative study of valence excited states.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.147-150
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• 1988

Since the integration level of VLSI circuits progresses very quickly, a highly reliable thin $SiO_2$ film is required to fabricate a small-geometry MOS device. In the present study we have attempted to eliminate the failure-causing defects that develop in thin oxide films during the oxidation step by performing a long-time preoxidation and postoxidation annealing. The TDDB test and the copper decoration method were used to calculate the oxide defects density of MOS device. The dielectric reliability of high-quality thin oxides have been studied by using the time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric -breakdown (Constant-stressed I-V) tests. Failure times against temperature and electric field are examined and acceleration factors are abtained for each parameter. Based on the data obtained, breakdown wearout limitation for thin oxide films is estimated.

• 대한전자공학회논문지
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• 제25권11호
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• pp.1329-1334
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• 1988

$NH_3-O_2$의 열반응에 의해 산화막을 성장시키는 새로운 방법을 소개하고, 기존의 건식산화방법을 이용한 $SiO_2$박막의 특성을 비교 설명하였다. $NH_3$의 유량에 따라서 박막의 성장비가 증가하고, 성장된 막의 구성성분이 건식산화때와 같음을 확인하였다. C-V특성곡선에서도 $Q_{OX}$와 $Q_{SS}$가 거의같았고 히스테리시스현상도 없었다. 또한 n-MOS트랜지스터를 제작하고 측정한 결과 $I_D$-$V_{DS}$특성곡선이 건식산화와 비교하여 우수함을 확인했다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1353-1354
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• 2007

폴리 실리콘 층의 유무에 따른 금속-옥사이드-반도체(MOS) 구조의 소자를 제작하였다. 터널링 산화막과 블로킹 산화막으로는 $Al_{2}O_{3}$ 층을 증착하였으며, 원자층 증착법을 이용하여 제작하였다. 터널링 산화막 층의 두께에 따른 I-V와 C-V 특성을 측정하였다. 전자들이 폴리 실리콘 층에 저장됨에 따라 N-형의 I-V 특성이 관찰되었다. C-V 측정 시에는 반시계 방향의 히스테리시스 특성을 나타내었으며, 전압이 증가할수록 플랫-밴드 전압 이동 폭이 더욱 증가하였다. 이러한 전기적 특성은 전압의 이동에 따른 전자들이 터널링 산화막 층을 통하여 폴리 실리콘 내부에 저장되기 때문이다. 이를 특성들은 폴리 실리콘의 전하 저장 가능성을 보여주는 것이며, 터널링 산화막 층의 두께에 따른 전기적 특성 변화도 관찰하였다.

• 대한전자공학회논문지
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• 제24권1호
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• pp.102-109
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• 1987

This study is carrier out to investigate the carrier injection and the characteristics of trapping for the CVD deposited Al2O3 film on Si substrates. Samples used are metal -Al2O3-Si Structure in which metal field plates are used with Aluminium or God. Canier injection and trapping, which result in flat band voltalge shift, occur at fields as low as 1~2 MV/cm. An approximate method is proposed for computing the location of the centroid of the trapped electrons in this paper. Results show that carriers are trapped near the injecting interface at fields less than about 5MV/cm. Because of continued charging, a steady state can not be reached. Therefore the unique I-V curve is obtained when the traps are initially empty. By utilization of applied voltage on each point of the fresh device sample, it is measured the I-V surves for two polarities of applied voltage. The current densities observed in the Al2O3 films are much larger than those obtained in SiO2.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.343-346
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• 1998

Ultra-thin gate oxide in MOS devices are subjected to high-field stress during device operation, which degrades the oxide and exentually causes dielectric breakdown. In this paper, we investigate the electrical properties of ultra-thin nitrided oxide (NO) and reoxidized nitrided oxide(ONO) films that are considered to be promising candidates for replacing conventional silicon dioxide film in ULSI level integration. We study vriations of I-V characteristics due to F-N tunneling, and time-dependent dielectric breakdown (TDDB) of thin layer NO and ONO depending on nitridation and reoxidation condition, and compare with thermal $SiO_{2}$. From the measurement results, we find that these NO and ONO thin films are strongly depending on its condition and that optimized reoxided nitrided oxides (ONO) films show superior dielectric characteristics, and breakdown-to-change ( $Q_{bd}$ ) performance over the NO films, while maintaining a similar electric field dependence compared to NO layer.

• 전자공학회논문지A
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• 제30A권2호
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• pp.53-63
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• 1993

Device degradations by the Fowler-Nordheim tunneling have been studide. The changes of device characteristics such as the threshold voltage, subthreshold slope, I-.or. curves have been measured after bidirectionally stressing n-channel MOSFET's and p-channel MOSFET's. Also the interface states have been directly measured by the charge pumping methodIt is shown that the change of interface states is determined by the number of hole carriers tunneling the gate oxide and electrons which are trapped in the gate oxide. Also, in this paper, we propose a model for device lifetime limited by the increase of interface states.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.