• 대한전자공학회논문지TC
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• 제45권3호
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• pp.1-6
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• 2008

본 논문에서는 2.4GHz 및 5GHz의 이중대역에서 동작하는 I/Q 모듈레이터를 설계하였다. 광대역 믹서에 $90^{\circ}$ 위상천이기를 이용하여 quadrature 신호를 입력하여 베이스밴드 신호를 변조된 RF 신호로 출력한다. 제안한 I/Q 모듈레이터의 변환 손실은 2.4GHz에서 약 15dB이고 5.8GHz 대역에서 약 16dB이다. 사이드밴드 억압특성은 2.4GHz/5GHz에서 각각 15dBc, 16dBc이며, carrier suppression은 두 대역에서 약 40dBc이다. 또한 11Mbps 의 QPSK 신호입력시의 EVM 특성은 2.4GHz에서 약 8.5%, 5GHz에서 10% 이며, 반송파 억압은 두 대역에서 40dB 이상으로, 무선 랜 신호를 인가시 출력 스펙트럼 규격을 만족하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1391-1392
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• 2008

The modulation quality of the I/Q modulator in a wireless transmitter usually affects system performance and it mostly depends on both a nonlinearity and a distortion, from the third order intermodulation(IM3) signal and the imperfection features such as an input amplitude error and a local phase error, respectively. This paper focused on how much the Single Sideband Ratio(SSR), which indicates the signal distortion, changes according to the variation of the imperfection features. Since a desired signal, side band and IM3 signals at the I/Q modulator output are also represented with those power series coefficients and the imperfection features, the effects of the imperfection features on SSR can be clearly analyzed.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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• pp.570-572
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• 2008

The modulation quality of the I/Q modulator in a wireless transmitter usually affects system performance and it mostly depends on both a nonlinearity and a distortion, from the third order intermodulation($IM_3$) signal and the error components such as an input amplitude error and a local phase error, respectively. This paper focused on how much the Single Sideband Ratio(SSR), which indicates the signal distortion, changes according to the variation of the error components. Consequently, since a desired signal, side band signal at the I/Q modulator output are also represented with those power series coefficients and the error components, the effects of the error components on SSR to meet the EVM specification of the WPAN can be clearly analyzed.

• 한국군사과학기술학회지
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• 제9권3호
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• pp.48-55
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• 2006

This paper describes the antenna based GPS anti-jamming technology called CRPA(Controlled Reception Pattern Antenna), which used $2{\times}2$ array elements. In this system, the main functions are the antenna complex weight control and the GPS digital I/Q VM(Vector Modulator). To update the VM's I/Q complex weights, the PC based DAC(Digital to Analog Converter) module was also used and the two analog output voltages were applied to the $2{\times}2$ array elements to synthesize the null pattern. In the study, we also simulated the $2{\times}2$ GPS array null patterns to compare the null depth with experimental results. The VM was also modified at the frequency of 1.575GHz for the GPS L1 and controlled by the PC based VM software.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1939_1941
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• 2009

The modulation quality of the RF transmitter in a wireless communication system usually affects system performance and it mostly depends on both a nonlinearity and a distortion, from the intermodulation products and the I/Q mismatch such as I/Q amplitude error and a local phase error, respectively. This paper focused on how much the error vector magnitude(EVM) which describes the modulation accuracy changes according to the variation of the I/Q mismatch components at I/Q modulator. For this work, the equation for the EVM including the I/Q mismatch components can be induced and calculated in accordance with the variation of the I/Q mismatch components. Consequently, the effect of I/Q mismatch components on the EVM, which is required in the transmitter specification of Personal Area Network, can be clearly analyzed.

• ETRI Journal
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• 제36권6호
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• Journal of Electrical Engineering and Technology
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• 제7권4호
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• pp.570-575
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• 2012

In a wireless communication RF transmitter, the output of a quadrature modulator (QM) is distorted by not only the linear imperfection features such as in/quadrature-phase (I/Q) input gain imbalance, local phase imbalance, and local gain imbalance but also the nonlinear imperfection features such as direct current (DC) offset and mixer nonlinearity related to in-band spurious signal. In this paper, we propose the unified QM model to analyze the combined effects of the linear and nonlinear imperfection features on the performance of the QM. The unified QM model consists of two identical nonlinear systems and modified I/Q inputs based on the two-port nonlinear mixer model. The unified QM model shows that the output signals can be expressed by mixer circuit parameters such as intercept point and gain as well as the imperfection features. The proposed approach is validated by not only simulation but also measurement.

• 전자공학회논문지A
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• 제33A권6호
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• pp.32-41
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• 1996

We propose the improved GMSK (gaussian-filtered minimum shift keying) quadrature modulator using the FIR(finite impulse response )filter whose coefficients are obtained form the differnce of phase response, and design its ASIC (applicaton specific integrated circuit) which can be used for GSM (global system for mobile communication) digital cellular system and DCS 1800 (digital cellular system at 1800MHz) personal communication system. Input data become quantized I and Q channel 10 bit signal through cosine and sine ROM mapping after being filtered by the FIR filter whose normalized bandwidth is 0.3 and designed by considering intersymbol interference as well as sampling ratio. These two signals become the GMSK modulated I and Q channel signal through DAC (digital-to-analog converter) and 7th order analog chebyshev LPF(low pass filter) respectively. The difference between the ideal analog signal and its digitized signal is analyzed in terms of sampling noise, quantization noise, truncation noise and coefficient noise. And the effect of the LPF following the DAC is considered. The ASIC design of the GMSK quadrature modulator is also confirmed by an experiment.

• 한국통신학회논문지
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• 제41권11호
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• pp.1566-1573
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• 2016

본 논문은 무인기(UAV) 기반 공중 네트워크 시스템을 위한 polyphase In-phase/Quadrature-phase(I/Q) 네트워크 기반 빔-포밍 수신부를 제안한다. 제안하는 polyphase I/Q 네트워크는 낮은 Q-factor와 높은 임피던스를 갖기 때문에 작은 손실로 벡터 변조기를 구동할 수 있다. 벡터 변조기는 가변 이득 증폭기(VGA)로 구성되며, In-phase 및 Quadrature-phase 위상 신호의 진폭 제어 및 벡터 합을 통해 위상을 가변한다. 제안하는 빔-포밍 수신부는 TSMC $0.18{\mu}m$ CMOS 공정을 통해 구현하였다. 프로토타입은 5-6GHz 주파수 대역(-40dB 입력)에서 검증하였다. 6bit 벡터 변조기 제어를 통해 $5.6^{\circ}$ LSB (least significant bit)로 $360^{\circ}$ 위상 가변이 가능하다. 위상 오차는 평균 $1.6^{\circ}$이며, 진폭 오차는 평균 0.3dB이다.

• 한국통신학회논문지
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• 제24권10A호
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• pp.1571-1578
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• 1999

본 논문은 Direct Sequence Code Division Multiple Access (DS-CDMA) Wireless Local Loop (WLL) 시스템의 Radio Transceiver Unit (RTU)를 위한 변조기 채널 카드와 변조기 VLSI 칩의 설계 및 구현에 대해서 서술했다. 변조기 채널 카드는 ASIC, FPGA 그리고 DSP를 이용하여 구현하였다. 구현된 변조기 ASIC칩은 ETRI가 제안한 Common Air Interface (CAI) 규격을 따랐고, 동작주파수는 32MHz, 회로의 크기는 40,000 게이트이다. 그리고 $0.6\mu\textrm{m}$ CMOS 공정으로 제작되었다. 본 변조기 ASIC 칩은 4개의 I,Q 채널을 처리할 수 있는 구조로 되어 있고 각 채널은 콘벌루션널 코딩, 블록 인터리빙, 스크램블링, 왈쉬 카버링, Pseudo Noise (PN) 확산 그리고 기저대역 필터링 기능 등을 포함한다. 변조기 채널 카드는 WLL 시스템 내 RTU의 서브 유니트의 하나이며 구현된 변조기 ASIC 및 채널 카드는 실제 WLL 시스템에 실장되어 그 성능 및 기능 요구사항을 만족함을 확인할 수 있었다.