• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• Journal of Korea Multimedia Society
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• v.5 no.1
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• pp.47-56
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• 2002

Previous buffer cache schemes for multimedia storage systems only exploited the sequential references of multimedia files and didn't consider looping references. However, in some video applications like foreign language learning, users mark the scene as loop area and then application automatically playbacks the scene several times. In this paper, we propose a new buffer replacement scheme, called HBM(Hybrid Buffer Management), for multimedia storage systems that have both sequential and looping references. Proposed scheme assumes that application layer informs reference pattern of files to file system. Then HBM applies an appropriate replacement policy to each file. Our simulation experiments show that HBM outperforms previous buffer cache schemes such as DISTANCE and LRU.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8B
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• pp.812-821
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• 2009

This paper proposes a novel dynamically reconfigurable switch for various multimedia applications in hybrid NoC systems. Current NoC systems, which adopt hybrid NoC structure with fixed switch and job distribution algorithms, require designers to precisely predict the property of applications to be processed. This paper proposes a reconfigurable switch which minimizes buffer overflow in various multimedia applications running on an NoC system. To verify the performance of the proposed system, we performed experiments on various multimedia applications running on embedded systems, such as MPEG4 and MP3 decoder, GPS positioning system, and OFDM demodulator. Experimental results show that buffer overflow has been decreased by 41.8% and 29.0%, respectively, when compared with NoC systems having sub-clusters with mesh or star topology. Power usage has been increased by 2.3% compared with hybrid NoC systems using fixed switches, and chip area has been increased from -0.6% to 5.7% depending on sub-cluster topology.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.151-160
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• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.209-218
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• 2016

This paper proposes a new lifetime aware buffer mapping method of a synchronous dataflow (SDF) graph on a hybrid memory system with DRAM and PRAM. Since the number of write operations on PRAM is limited, the number of written samples on PRAM is minimized to maximize the lifetime of PRAM. We improve the utilization of DRAM by mapping more buffers on DRAM through buffer sharing. The problem is formulated formally and solved by an optimal approach of an answer set programming. In experiment, the buffer mapping method with buffer sharing improves the PRAM lifetime by 63%.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.57-64
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• 2021

The domestic semiconductor industry can produce various products that will satisfy customer needs by diversifying assembly parts and increasing compatibility between them. It is necessary to improve the production line as a method to reduce the work-in-process inventory (WIP) in the assembly line, the idle time of the worker, and the idle time of the process. The improvement of the production line is to balance the capabilities of each process as a whole, and to determine the timing of product input or the order of the work process so that the time required between each process is balanced. The purpose of this study is to find the optimal WIP and buffer size through SA (Simulated Annealing) that minimizes lead time while matching the number of two parts in a parallel assembly line with bottleneck process. The WIP level and buffer size obtained by the SA algorithm were applied to the CONWIP and DBR systems, which are the existing production systems, and the simulation was performed by applying them to the new hybrid production system. Here, the Hybrid method is a combination of CONWIP and DBR methods, and it is a production system created by setting new rules. As a result of the Simulation, the result values were derived based on three criteria: lead time, production volume, and work-in-process inventory. Finally, the effect of the hybrid production method was verified through comparative analysis of the result values.

• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.61-67
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• 2020

This paper is to propose a hybrid memory adaptor using next-generation nonvolatile memory devices such as phase-change memory to improve the performance limitations of OpenStack-based object storage systems. The proposed system aims to improve the performance of the account and container servers for object metadata management. For this, the proposed system consists of locality-based dynamic page buffer, write buffer, and nonvolatile memory modules. Experimental results show that the proposed system improves the hit rate by 5.5% compared to the conventional system.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.287-299
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• 2000

In this paper, we classify multicast methods into three categories, i.e., tree-based, path-based, and hybrid-based multicasts, for a multicomputer employing the bidirectional torus network and wormhole routing. We propose the dynamic partition multicast routing (DPMR) as a path-based algorithm. As a hybrid-based algorithm, we suggest the hybrid multicast routing (HMR), which employs the tree-based approach in the first phase of routing and the path-based approach in the second phase. Performance is measured in terms of the average latency for various message length to compare three multicast routing algorithms. We also compare the performance of wormhole routing having variable buffer size with virtual cut-through switching. The message latency for each switching method is compared using the DPMR algorithm to evaluate the buffer size trade-off on the performance.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.29 no.4
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• pp.100-106
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• 2006

We analyze a voice/data integrated traffic model of the cellular mobile communication system with hybrid guard channels for voice and handoff calls. In a multi-service integrated wireless environment, quality of service guarantee is crucial for smooth transportation of real time information. Real time voice traffic requires a guaranteed upper bounded on both delay and packet error rate, whereas data traffic does not. Voice traffic has high transmission priority over data packets. Thus one of the important problems is the design of admission control schemes which can efficiently accommodate the differential quality of service requirements. In this paper, a hybrid guard channel scheme is considered in which arriving calls are assigned channels as long as the number of busy channels in the cell is below a predetermined first threshold. When the number of busy channels reaches the first threshold, new originating data calls are queued in the infinite data buffer. Then reaches second threshold, only handoff calls are assigned the remaining channels and new originating voice calls are blocked. We evaluate the system by a two-dimensional Markov chain approach and generating function method and obtain performance measures included blocking probability and forced termination probability.