• 한국전기전자재료학회논문지
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• 제14권10호
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• pp.792-795
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• 2001

we present a electrical transport(resistivity, Hall effect) measurements in varying temperature ranges between 78K and 300K on HoSi$_2$ composites by hot-pressed sintering. It has been found that this sintered HoSi$_2$ has a orthorhombic structure, and lattices constant is a=9.8545$\AA$, b=7.7935$\AA$, c=7.8071$\AA$. The measured electrical resistivity is about 1.608$\Omega$ cm and carrier mobility is about 6.9$\times$10$^{1}$cm $^{2}$V.sec at low room temperature. The Hall effect shows a n-type conductivity in the sintered HoSi$_2$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.328.1-328.1
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• 2014

MOSFET degradation의 대부분은 hot-carrier injection에 의한 interface state (Dit)의 생성에서 비롯되며 따라서 본 연구에서는 신뢰성에 대한 한 가지 방법으로 Charge pumping method를 이용하여 MOSFET의 interface trap(Dit)의 변화를 측정하였다. 소스와 드레인을 ground로 묶고 게이트에 펄스를 인가한 후 Icp를 측정하여 Dit를 추출하였다. 온도를 293~343 K까지 5 K씩 가변했을 때 293K의 Icp(${\mu}A$)는 0.12 nA 313 K는 0.112 nA 343 K는 0.926 nA이며 Dit (cm-1/eV-1)는 $1.61{\times}10^{12}$ (Cm-2/eV-1) $1.49{\times}10^{12}$ (Cm-2/eV-1) $1.23{\times}10^{12}$ (Cm-2/eV-1)이다. 측정결과 Dit는 Icp가 높은 지점에서 추출되며 온도가 높아지게 되면 Icp전류가 낮아지고 Dit가 줄어드는 것을 볼 수 있다. 온도가 올라가게 되면 carrier들이 trap 준위에서 conduction band 위쪽에 이동하게 되어서 interface에 trap되는 양이 작아지게 된다. 그래서 이때 Icp를 이용해 추출한 Dit 는 실제로 trap의 양이 줄어든 것이 아니라 Thermal excess 현상으로 인해 측정되는 Icp의 양이 줄어든 것으로 분석할 수 있다.

• Transactions on Electrical and Electronic Materials
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• 제5권5호
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• pp.173-179
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• 2004

The influence of heavily Si impurity doping in the GaN barrier of InGaN/GaN multi-quantum well structures of blue light emitting diodes were investigated by growing samples in metal-organic chemical vapor deposition. The delta-doped sample was compared to the sample with the undoped barrier. The delta-doped sample shows the tunneling behavior and forms the energy level of 0.32 eV for tunneling and the photoemission of the 450-nm band. The photo-luminescence shows the blue-shifted broad band of the radiative transition due to the inclusion of Si delta-doped layer indicating that the delta doping effect acts to form the higher energy level than that of quantum well. The dislocation may provide the carrier tunneling channel and plays as a source of acceptor. During the tunneling of hot carrier, there was no light emission.

• 대한전자공학회논문지SD
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• 제43권3호
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• pp.1-8
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• 2006

본 논문에서는 채널 stress에 따른 Nano-scale CMOSFET의 소자 및 신뢰성 (HCI, NBTI)특성을 분석하였다. 잘 알려져 있듯이 NMOS는 tensile, PMOS는 compressive stress가 인가된 경우에 소자의 특성이 개선되었으며, 이는 전자와 정공의 이동도 증가에 의한 것임을 확인하였다. 그러나 신뢰성인 경우에는 소자 특성과는 다른 특성을 나타냈는데, NMOS와 PMOS 모두 tensile stress가 인가된 경우에 hot carrier 특성이 더 열화 되었으며, PMOS의 PBTI 특성도 tensile에서 더 열화 되었음을 확인하였다. 신뢰성을 분석한 결과, 채널의 tensile stress로 인하여 $Si/SiO_2$ 계면에서 interface trap charge의 생성과 산화막 내 positive fixed charge의 생성에 많은 영향을 끼침을 알 수 있었다. 그러므로 나노급 CMOSFET에 적용되는 strained-silicon MOSFET의 개발을 위해서는 소자의 성능 뿐 만 아니라 신뢰성 또한 고려되어야 한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.164-164
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• 2013

Among multicomponent nanostructures, hybrid nanocatalysts consisting of metal nanoparticle-semiconductor junctions offer an interesting platform to study the role of metal-oxide interfaces and hot electron flows in heterogeneous catalysis. In this study, we report that hot carriers generated upon photon absorption significantly impact the catalytic activity of CO oxidation. We found that Pt-CdSe-Pt nanodumbbells exhibited a higher turnover frequency by a factor of two during irradiation by light with energy higher than the bandgap of CdSe, while the turnover rate on bare Pt nanoparticles didn't depend on light irradiation. We also found that Pt nanoparticles deposited on a GaN substrate under light irradiation exhibit changes in catalytic activity of CO oxidation that depends on the type of doping of the GaN. We suppose that hot electrons are generated upon the absorption of photons by the semiconducting nanorods or substrates, whereafter the hot electrons are injected into the Pt nanoparticles, resulting in the change in catalytic activity. We discuss the possible mechanism for how hot carrier flows generated during light irradiation affect the catalytic activity of CO oxidation.

• 대한조선학회논문집
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• 제45권3호
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• pp.296-302
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• 2008

Recently, a mesh-size insensitive structural stress definition (structural stress method) is proposed that gives a stress state at weld toe with a relatively large mesh size. The structural stress definition is based on the elementary structural mechanics theory and provides an effective measure of a stress state in front of weld toe. In this study, a fatigue strength assessment for a side shell connection of a container vessel using both the hot spot stress and the Battelle structural stress method was carried out. A consistent approach to compute the extrapolated hot spot stress for design purpose is described and current fatigue guidance is evaluated. Fatigue strength predicted by the two methodologies, e.g. hot spot stress and structural stress approaches, at hot spot locations of a typical ship structure are compared and discussed.

• 한국재료학회지
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• 제14권7호
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• pp.516-521
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• 2004

We applied a deuterium plasma treatment to the surface of polycrystalline silicon films using PECVD and observed the change with AFM, XRD, ET-IR, and SIMS measurement. A bias temperature stressing (BTS) test was carried out to evaluate the reliability of the thin-film transistors (TFT). TFTs with channel lengths as small as 2 ${\mu}m$ were electrically stressed fer up to 1000 sec at room temperature. From the parameter variation such as s-factor, leakage current and on/off ratio, we suggest that the deuterium plasma treatment suppress the hot carrier effect and improve the stability of TFTs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• International Journal of Naval Architecture and Ocean Engineering
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• 제7권1호
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• pp.10-24
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• 2015

This study introduces a fatigue assessment procedure using mesh-insensitive structural stress method based on the Common Structural Rules for Bulk Carriers by considering important factors, such as mean stress and thickness effects. The fatigue assessment result of mesh-insensitive structural stress method have been compared with CSR procedure based on equivalent notch stress at major hot spot points in the area near the ballast hold for a 180 K bulk carrier. The possibility of implementing mesh-insensitive structural stress method in the fatigue assessment procedure for ship structures is discussed.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 추계종합학술대회
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• pp.656-659
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• 2001

최근 반도체 기술의 발달로 소자의 크기가 줄어들면서 높은 에너지를 갖는 핫 캐리어 전송 해석이 매우 중요하게 되었다. Auger 과정과는 반대인 임팩트이온화현상은 핫 캐리어에 의한 산란에 의하여 전자-정공쌍을 생성하는 과정으로 소자의 전송특성 해석을 위한 시뮬레이션에 정확한 임팩트 이온화모델이 필수적이다. 본 연구에서는 Monte Carlo 시뮬레이터를 이용한 임팩트이온화 모델과 TCAD 그리고 Micro-Tec을 이용한 임팩트이온화 모델을 분석하여 보다 정확한 임팩트이온화 모델을 제시하고자 한다.