• Title/Summary/Keyword: Hot Carrier

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Electrical Properties of Sintered $HoSi_2$ ($HoSi_2$소결체의 전기적 특성 연구)

  • 이우선;김형곤;김남오
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.10
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    • pp.792-795
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    • 2001
  • we present a electrical transport(resistivity, Hall effect) measurements in varying temperature ranges between 78K and 300K on HoSi$_2$ composites by hot-pressed sintering. It has been found that this sintered HoSi$_2$ has a orthorhombic structure, and lattices constant is a=9.8545$\AA$, b=7.7935$\AA$, c=7.8071$\AA$. The measured electrical resistivity is about 1.608$\Omega$ cm and carrier mobility is about 6.9$\times$10$^{1}$cm $^{2}$V.sec at low room temperature. The Hall effect shows a n-type conductivity in the sintered HoSi$_2$.

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Charge Pumping Method를 이용한 N-type MOSFET의 Interface Trap(Dit) 분석

  • Go, Seon-Uk;Kim, Sang-Seop;Choe, Byeong-Deok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.328.1-328.1
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    • 2014
  • MOSFET degradation의 대부분은 hot-carrier injection에 의한 interface state (Dit)의 생성에서 비롯되며 따라서 본 연구에서는 신뢰성에 대한 한 가지 방법으로 Charge pumping method를 이용하여 MOSFET의 interface trap(Dit)의 변화를 측정하였다. 소스와 드레인을 ground로 묶고 게이트에 펄스를 인가한 후 Icp를 측정하여 Dit를 추출하였다. 온도를 293~343 K까지 5 K씩 가변했을 때 293K의 Icp(${\mu}A$)는 0.12 nA 313 K는 0.112 nA 343 K는 0.926 nA이며 Dit (cm-1/eV-1)는 $1.61{\times}10^{12}$ (Cm-2/eV-1) $1.49{\times}10^{12}$ (Cm-2/eV-1) $1.23{\times}10^{12}$ (Cm-2/eV-1)이다. 측정결과 Dit는 Icp가 높은 지점에서 추출되며 온도가 높아지게 되면 Icp전류가 낮아지고 Dit가 줄어드는 것을 볼 수 있다. 온도가 올라가게 되면 carrier들이 trap 준위에서 conduction band 위쪽에 이동하게 되어서 interface에 trap되는 양이 작아지게 된다. 그래서 이때 Icp를 이용해 추출한 Dit 는 실제로 trap의 양이 줄어든 것이 아니라 Thermal excess 현상으로 인해 측정되는 Icp의 양이 줄어든 것으로 분석할 수 있다.

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Inclusion of Silicon Delta-doped Two-dimensional Electron Gas Layer on Multi-quantum Well Nano-structures of Blue Light Emitting Diodes

  • Kim, Keun-Joo
    • Transactions on Electrical and Electronic Materials
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    • v.5 no.5
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    • pp.173-179
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    • 2004
  • The influence of heavily Si impurity doping in the GaN barrier of InGaN/GaN multi-quantum well structures of blue light emitting diodes were investigated by growing samples in metal-organic chemical vapor deposition. The delta-doped sample was compared to the sample with the undoped barrier. The delta-doped sample shows the tunneling behavior and forms the energy level of 0.32 eV for tunneling and the photoemission of the 450-nm band. The photo-luminescence shows the blue-shifted broad band of the radiative transition due to the inclusion of Si delta-doped layer indicating that the delta doping effect acts to form the higher energy level than that of quantum well. The dislocation may provide the carrier tunneling channel and plays as a source of acceptor. During the tunneling of hot carrier, there was no light emission.

Characterization of the Dependence of the Device on the Channel Stress for Nano-scale CMOSFETs (Nano CMOSFET에서 Channel Stress가 소자에 미치는 영향 분석)

  • Han In-Shik;Ji Hee-Hwan;Kim Kyung-Min;Joo Han-Soo;Park Sung-Hyung;Kim Young-Goo;Wang Jin-Suk;Lee Hi-Deok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.3 s.345
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    • pp.1-8
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    • 2006
  • In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

Influence of Charge Transport of Pt-CdSe-Pt Nanodumbbells and Pt Nanoparticles/GaN on Catalytic Activity of CO Oxidation

  • Kim, Sun Mi;Lee, Seon Joo;Kim, Seunghyun;Kwon, Sangku;Yee, Kiju;Song, Hyunjoon;Somorjai, Gabor A.;Park, Jeong Young
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.164-164
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    • 2013
  • Among multicomponent nanostructures, hybrid nanocatalysts consisting of metal nanoparticle-semiconductor junctions offer an interesting platform to study the role of metal-oxide interfaces and hot electron flows in heterogeneous catalysis. In this study, we report that hot carriers generated upon photon absorption significantly impact the catalytic activity of CO oxidation. We found that Pt-CdSe-Pt nanodumbbells exhibited a higher turnover frequency by a factor of two during irradiation by light with energy higher than the bandgap of CdSe, while the turnover rate on bare Pt nanoparticles didn't depend on light irradiation. We also found that Pt nanoparticles deposited on a GaN substrate under light irradiation exhibit changes in catalytic activity of CO oxidation that depends on the type of doping of the GaN. We suppose that hot electrons are generated upon the absorption of photons by the semiconducting nanorods or substrates, whereafter the hot electrons are injected into the Pt nanoparticles, resulting in the change in catalytic activity. We discuss the possible mechanism for how hot carrier flows generated during light irradiation affect the catalytic activity of CO oxidation.

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A Comparative Study for the Fatigue Assessment of Side Shell Longitudinals on 8,100 TEU Container Carrier using Hot Spot Stress and Structural Stress Approaches (구조응력 및 핫스팟 응력을 이용한 8,100 TEU 컨테이너선 선측 종늑골구조의 피로 강도 평가에 대한 비교 연구)

  • Kim, Seong-Min;Kim, Myung-Hyun;Kang, Sung-Won;Pyun, Jang-Hoon;Kim, Young-Nam;Kim, Sung-Geun;Lee, Kyong-Eon;Kim, Gyeng-Rae
    • Journal of the Society of Naval Architects of Korea
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    • v.45 no.3
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    • pp.296-302
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    • 2008
  • Recently, a mesh-size insensitive structural stress definition (structural stress method) is proposed that gives a stress state at weld toe with a relatively large mesh size. The structural stress definition is based on the elementary structural mechanics theory and provides an effective measure of a stress state in front of weld toe. In this study, a fatigue strength assessment for a side shell connection of a container vessel using both the hot spot stress and the Battelle structural stress method was carried out. A consistent approach to compute the extrapolated hot spot stress for design purpose is described and current fatigue guidance is evaluated. Fatigue strength predicted by the two methodologies, e.g. hot spot stress and structural stress approaches, at hot spot locations of a typical ship structure are compared and discussed.

A Study on the Effect of Plasma Deuterium Treatment on Reliability of Poly-Silicon Thin Film Transistors (중수소 프라즈마 처리가 다결정 실리콘 TFT의 안정성에 미치는 영향에 관한 연구)

  • Sohn Song Ho;Bae S. C.;Kim Donghwan
    • Korean Journal of Materials Research
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    • v.14 no.7
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    • pp.516-521
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    • 2004
  • We applied a deuterium plasma treatment to the surface of polycrystalline silicon films using PECVD and observed the change with AFM, XRD, ET-IR, and SIMS measurement. A bias temperature stressing (BTS) test was carried out to evaluate the reliability of the thin-film transistors (TFT). TFTs with channel lengths as small as 2 ${\mu}m$ were electrically stressed fer up to 1000 sec at room temperature. From the parameter variation such as s-factor, leakage current and on/off ratio, we suggest that the deuterium plasma treatment suppress the hot carrier effect and improve the stability of TFTs.

Analysis and Degradation of leakage Current in submicron Device (미세소자에서 누설전류의 분석과 열화)

  • 배지철;이용재
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1996.11a
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    • pp.113-116
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    • 1996
  • The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

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Incorporating mesh-insensitive structural stress into the fatigue assessment procedure of common structural rules for bulk carriers

  • Kim, Seong-Min;Kim, Myung-Hyun
    • International Journal of Naval Architecture and Ocean Engineering
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    • v.7 no.1
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    • pp.10-24
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    • 2015
  • This study introduces a fatigue assessment procedure using mesh-insensitive structural stress method based on the Common Structural Rules for Bulk Carriers by considering important factors, such as mean stress and thickness effects. The fatigue assessment result of mesh-insensitive structural stress method have been compared with CSR procedure based on equivalent notch stress at major hot spot points in the area near the ballast hold for a 180 K bulk carrier. The possibility of implementing mesh-insensitive structural stress method in the fatigue assessment procedure for ship structures is discussed.

Analysis of Impact ionization Model for Nano structure Silicon device (나노구조 실리콘 소자의 임팩트이온화 모델 분석)

  • 고석웅;임규성;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.10a
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    • pp.656-659
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    • 2001
  • Recently, as device techniques are advancing and its size become smaller, the hot carriers transport analysis has more important. Impact ionization(I.I.) effect is electron-hole pair generation process by the dispersion of hot carrier in the contrast with Auger process. Complete I.I. model is essential to simulate and analysis the device transport characteristics. In the study, we will try to analysis I.I. models using Monte Carlo simulator, TCAD and Micro-Tec and present more accurate I.I. model.

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