• 한국산학기술학회논문지
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• 제22권1호
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• pp.321-326
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• 2021

본 연구는 웨이퍼를 적재할 때 웨이퍼의 손상을 최소화 시키기 위한 기술이다. 반도체와 솔라셀에 이용되는 두께가 얇은 웨이퍼는 적재된 웨이퍼 사이의 표면 장력에 의해 웨이퍼의 분리를 어렵게 만들어 웨이퍼의 표면에 손상을 줄 수 있다. 이러한 웨이퍼의 손상을 최소화시키는 기술은 압축 공기를 웨이퍼 쪽으로 분사하고, 미소의 수평 이동 기구를 동시에 적용하는 것이다. 연구에 사용된 주요 실험 인자는 웨이퍼의 공급 속도, 압축 공기의 노즐 압력, 그리고 흡착 헤드의 흡착 시간이다. 실험 결과, 동일한 노즐 압력에서 웨이퍼의 공급 속도가 빠를수록 파손율이 증가하고, 동일한 공급 속도에서는 노즐 압력이 낮을수록 파손율이 증가한다. 그리고, 웨이퍼를 흡착시키데 필요한 시간은 어느 수준 이상이면 웨이퍼의 공급 속도에 따른 파손율에는 큰 영향을 미치지 않는다. 본 연구의 실험 범위 안에서 최적의 실험 조건은 웨이퍼의 공급 속도 600 ea/hr, 압축 공기의 노즐 압력 0.55 MPa, 흡착 헤드의 흡착 시간 0.9 sec 이다. 또한, 반복성능 실험을 통해 개선된 기술은 웨이퍼의 파손율을 최소화시킬 수 있음을 보여 주었다.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1996년도 춘계학술발표회논문집(2)
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• pp.247-253
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• 1996

The Interfacial friction factor for the countercurrent stratified air-wafer flow has been experimentally investigated in nearly horizontal and inclined pipes. The presence of the hydraulic jump may significantly affect both the flow pattern and the interfacial friction factor. The measured values of f$_{i}$ in nearly horizontal and two inclined pipes are of the same order of magnitude but the dependencies of the air and water velocities are slightly different.t.

• Journal of Electrical Engineering and Technology
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• 제5권2호
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• pp.337-341
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• 2010

In this paper, an extremely low voltage operated micro corner cube retroreflector (CCR) was fabricated for free-space optical communication applications by using bulk silicon micromachining technologies. The CCR was comprised of an orthogonal vertical mirror and a horizontal actuated mirror. For low voltage operation, the horizontal actuated mirror was designed with two PZT cantilever actuators, torsional bars, hinges, and a mirror plate with a size of $400{\mu}m{\times}400{\mu}m$. In particular, the torsional bars and hinges were carefully simulated and designed to secure the flatness of the mirror plate by using a finite element method (FEM) simulator. The measured tilting angle was approximately $2^{\circ}$ at the applied voltage of 5 V. An orthogonal vertical mirror with an extremely smooth surface texture was fabricated using KOH wet etching and a double-SOI (silicon-on-insulator) wafer with a (110) silicon wafer. The fabricated orthogonal vertical mirror was comprised of four pairs of two mutually orthogonal flat mirrors with $400{\mu}m4 (length) $\times400{\mu}m$ (height) $\times30{\mu}m$ (thickness). The cross angles and surface roughness of the orthogonal vertical mirror were orthogonal, almost $90^{\circ}$ and 3.523 nm rms, respectively. The proposed CCR was completed by combining the orthogonal vertical and horizontal actuated mirrors. Data transmission and modulation at a frequency of 10 Hz was successfully demonstrated using the fabricated CCR at a distance of approximately 50 cm.

• 한국결정성장학회지
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• 제11권5호
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• pp.218-223
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• 2001

수평 Bridgman 방법으로 성장한 사파이어 인고트를 절단 연마한 후, 사파이어 결정기판의 표면을 우레탄 천 위에서 실리카 졸을 사용하여 폴리싱하였다. 표면의 결정성을 X-선 회절을 통하여 조사하였으며, 2중 결정회절에 의한 반치폭은 200~400 arcsec을 가지며, 결정 인고트의 절편화 또는 양면 연삭 연마에 따른 잔류응력에 의한 표면에서의 기계적인 스트레스에 의해 결정성이 손상되어진다. 화학-기계적인 폴리싱공정을 수행한 수에 표면처리로 $1,200^{\circ}C$로 4시간 열처리 및 산처리를 연속적으로 수행할 경우 결정성이 반치폭 8.3 arcsec까지 줄어들어 향상됨을 확인하였다.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.759-762
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• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

• 한국재료학회지
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• 제20권12호
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• pp.645-648
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• 2010

The structure and morphology of epitaxial layer defects in epitaxial Si wafers produced by the Czochralski method were studied using focused ion beam (FIB) milling, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). Epitaxial growth was carried out in a horizontal reactor at atmospheric pressure. The p-type Si wafers were loaded into the reactor at about $800^{\circ}C$ and heated to about $1150^{\circ}C$ in $H_2$. An epitaxial layer with a thickness of $4{\mu}m$ was grown at a temperature of 1080-$1100^{\circ}C$. Octahedral void defects, the inner walls of which were covered with a 2-4 nm-thick oxide, were surrounded mainly by $\{111\}$ planes. The formation of octahedral void defects was closely related to the agglomeration of vacancies during the growth process. Cross-sectional TEM observation suggests that the carbon impurities might possibly be related to the formation of oxide defects, considering that some kinds of carbon impurities remain on the Si surface during oxidation. In addition, carbon and oxygen impurities might play a crucial role in the formation of void defects during growth of the epitaxial layer.

• 한국입자에어로졸학회지
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• 제18권4호
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• pp.129-136
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• 2022

The line width of circuits in semiconductor devices continues to decrease down to a few nanometers. Since nanoparticles attached to the patterned wafer surface may cause malfunction of the devices, it is crucial to remove the contaminant nanoparticles. Physical cleaning that utilizes momentum of liquid for detaching solid nanoparticles has recently been tested in place of the conventional chemical method. Dropwise impaction has been employed to increase the removal efficiency with expectation of more efficient momentum exchange. To date, most of relevant studies have been focused on drop spreading behavior on a horizontal surface in terms of maximum spreading diameters and average spreading velocity of drop. More important is the local liquid velocity at the position of nanoparticle, very near the surface, rather than the vertical average value. In addition, there are very scarce existing studies dealing with microdroplet impaction that may be desirable for minimizing pattern demage of the wafer. In this study, we investigated the local velocity distribution in spreading liquid film under various impaction conditions through the CFD simulation. Combining the numerical results with the particle removal model, we estimated an effective cleaning diameter (ECD), which is a measure of the particle removal capacity of a single drop, and presented the predicted ECD data as a function of droplet's velocity and diameter particularly when the droplets are microns in diameter.

• Applied Science and Convergence Technology
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• 제26권6호
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• pp.189-194
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• 2017

Effects of gas injection scheme and rf driving current configuration in a dual turn inductively coupled plasma (ICP) system were analyzed by 3D numerical simulation using CFD-ACE+. Injected gases from a tunable gas nozzle system (TGN) having 12 horizontal and 12 vertical nozzles showed different paths to the pumping surface. The maximum velocity from the nozzle reached Mach 2.2 with 2.2 Pa of Ar. More than half of the injected gases from the right side of the TGN were found to go to the pump without touching the wafer surface by massless particle tracing method. Gases from the vertical nozzle with 45 degree slanted angle soared up to the hottest region beneath the ceramic lid between the inner and the outer rf turn of the antenna. Under reversed driving current configuration, the highest rf power absorption region were separated into the two inner islands and the four peaked donut region.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.276-279
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• 2004

Plasma enhanced chemical vapor deposition (PECVD) of silicon nitride (SiN) is a proven technique for obtaining layers that meet the needs of surface passivation and anti-reflection coating. In addition, the deposition process appears to provoke bulk passivation as well due to diffusion of atomic hydrogen. This bulk passivation is an important advantage of PECVD deposition when compared to the conventional CVD techniques. A further advantage of PECVD is that the process takes place at a relatively low temperature of 300t, keeping the total thermal budget of the cell processing to a minimum. In this work SiN deposition was performed using a horizontal PECVD reactor system consisting of a long horizontal quartz tube that was radiantly heated. Special and long rectangular graphite plates served as both the electrodes to establish the plasma and holders of the wafers. The electrode configuration was designed to provide a uniform plasma environment for each wafer and to ensure the film uniformity. These horizontally oriented graphite electrodes were stacked parallel to one another, side by side, with alternating plates serving as power and ground electrodes for the RF power supply. The plasma was formed in the space between each pair of plates. Also this paper deals with the fabrication of multicrystalline silicon solar cells with PECVD SiN layers combined with high-throughput screen printing and RTP firing. Using this sequence we were able to obtain solar cells with an efficiency of 14% for polished multi crystalline Si wafers of size 125 m square.