• Title/Summary/Keyword: Holding Voltage

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Fast Switching Properties of TN Cell With Graphene Quantum Dots (그라핀 양자점을 도핑한 TN 셀의 고속 스위칭 특성)

  • Kim, Dai-Hyun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.2
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    • pp.110-114
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    • 2014
  • In this study, we report the doping effect of graphene quantum dots (QDs) in nematic liquid crystal (NLC) system on rubbed polyimide (PI) surface. The good LC alignment and high thermal stability in QD-LC cell system on rubbed PI surfaces can be measured. Also, the low threshold voltage of QD-TN cell was observed about 2.77 V. The fast response time of 13.2 ms for QD-TN cell can be achieved. Finally, the good voltage holding ratio of QD-TN cell on rubbed PI surface was measured.

Improvement of ESD (Electrostatic Discharge) Protection Performance of NEDSCR (N-Type Extended Drain Silicon Controlled Rectifier) Device using CPS (Counter Pocket Source) Ion Implantation (CPS 이온주입을 통한 NEDSCR 소자의 정전기 보호 성능 개선)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.8 no.1
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    • pp.45-53
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    • 2013
  • An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.

Analysis of a Parasitic-Diode-Triggered Electrostatic Discharge Protection Circuit for 12 V Applications

  • Song, Bo Bae;Lee, Byung Seok;Yang, Yil Suk;Koo, Yong-Seo
    • ETRI Journal
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    • v.39 no.5
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    • pp.746-755
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    • 2017
  • In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

Quench Analysis and Operational Characteristics of the Quench Detection System for the KSTAR PF Superconducting Coils (펄스전류 운전에 따른 KSTAR PF 초전도자석의 퀜치 분석 및 퀜치 검출 시스템 운전 특성)

  • Chu, Y.;Yonekawa, H.;Kim, Y.O.;Park, K.R.;Lee, H.J.;Oh, Y.K.
    • Progress in Superconductivity and Cryogenics
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    • v.11 no.3
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    • pp.20-25
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    • 2009
  • The quench detection system of the KSTAR (Korea Superconducting Tokamak Advanced Research) primarily uses the resistive voltage measurement due to a quench. This method is to detect the resistive voltage generated by a quench, which is continuously maintained above the preset voltage threshold for a given holding time. As the KSTAR PF (Poloidal Field) coils are operated in the pulse current mode, the large inductive voltages are generated. Therefore the voltage threshold and the quench holding time should be determined by considering both the inductive voltages measured during the operation, and the maximum conductor temperature rise through the quench analysis. In this paper, the compensation methods for minimizing the inductive voltages are presented for the KSTAR PF coils. The quench hot spot analysis of the PF coils was carried out by the analytical and numerical methods for determining the proper values of the quench voltage threshold and the allowable quench protection delay time.

식물세포의 관류배양을 위한 초음파 분리기의 개발

  • Gu, Yeong-Han;Jo, Gyu-Heon
    • 한국생물공학회:학술대회논문집
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    • 2000.11a
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    • pp.402-404
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    • 2000
  • In this study, we have developed an ultrasonic separation system for plant cells and its operating conditions in terms of voltage, flow rate and concentration were examined. For plant cell, the operation of ultrasonic separator highly depended on concentration of cells. Holding capacity highly depended on flow rate in chamber. Optimum voltage was 30V in high density culture

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Decrease of PEMFC Performance by SO2 in Air (공기 중 SO2에 의한 고분자전해질 연료전지의 성능 감소)

  • Lee, Ho;Song, Jinhoon;Kim, Kijoong;Kim, Saehoon;Ahn, Byungki;Lim, Taewon;Park, Kwonpil
    • Korean Chemical Engineering Research
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    • v.48 no.3
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    • pp.311-315
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    • 2010
  • The effects of $SO_2$ on the performance of proton exchange membrane(PEMFC) were investigated by introduction air containing $SO_2$ into cathode inlet of PEMFC. And the recovery of the cell performance by applying clean air, cycle voltammetry(CV) and high voltage holding following exposure contaminated air was studied. The $SO_2$ concentration range used in the experiments was from 20 ppb to 1.3 ppm. The performance degradation and recovery were measured by constant-current discharging, I-V polarization and electrochemical impedance spectroscopy(EIS). The cell voltage gradually decayed with time and decreased by 17 mV after 200 hours of 20 ppb $SO_2$ injection. The cell performance can be recovered partially by clean air flushing, CV and high voltage holding due to desorption of S from Pt catalyst.

A Study on SCR-Based ESD Protection Circuit with PMOS (PMOS가 삽입된 SCR 기반의 ESD 보호 회로에 관한 연구)

  • Kwak, Jae-Chang
    • Journal of IKEEE
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    • v.23 no.4
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    • pp.1309-1313
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    • 2019
  • In this paper, the electrical characteristics of Gate grounded NMOS(GGNMOS), Lateral insulated gate bipolar transistor(LIGBT), Silicon Controlled Rectifier(SCR), and Proposed ESD protection device were compared and analyzed. First, the trigger voltage and holding voltage were verified by simulating the I-V characteristic curve for each device. After that, the robustness was confirmed by HBM 4k simulation for each device. As a result of HBM 4k simulation, the maximum temperature of the proposed ESD protection device is lower than that of GGNMOS and GGLIGBT and SCR, which means that the robustness is improved, which means that the ESD protection device is excellent in terms of reliability.

A Study on ESD Protection Circuit for 2-Stack Structure Design Based on LVTSCR (LVTSCR 기반의 2-Stack 구조 설계를 위한 ESD 보호회로에 관한 연구)

  • Seo, Jeong-Yun;Do, Kyoung-Il;Chae, Hee-Guk;Seo, Jeong-Ju;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.22 no.3
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    • pp.836-841
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    • 2018
  • In this paper, This paper is based on the conventional ESD protection circuits SCR and LVTSCR. Also, the SCR-based ESD protection circuit, which is different from the conventional structure, is presented and tested for variations in the trigger voltage and holding voltage. Due to the insertion of additional N +, P + regions, the newly added SCR-based protection circuit have improved electrical characteristics. To discuss the electrical characteristics of the proposed circuit, Synopsys T-CAD simulation data was shown.

Latchup Characteristics of N-Type SCR Device for ESD Protection (정전기 보호를 위한 n형 SCR 소자의 래치업 특성)

  • Seo, Y.J.;Kim, K.H.;Lee, W.S.
    • Proceedings of the KIEE Conference
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    • 2006.07c
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    • pp.1372-1373
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    • 2006
  • An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, a modified NSCR_PPS device with proper junction/channel engineering demonstrates highly latchup immune current- voltage characteristics.

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Dielecrtric and Voltage Holding Properties of the Half-V-shaped Switching Ferroelectric Liquid Crystal Mode Driven by Active Matrix

  • Choi, Suk-Won;Kim, Hong-Chul;Jeong, Woo-Nam;Seo, Chang-Ryong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.1121-1124
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    • 2003
  • For high quality displays, analog responding liquid crystals with spontaneous polarization ($P_{s}$) need to be coupled with active matrix driving schemes. We have characterized the half-V-shaped switching ferroelectric liquid crystal mode (half-V FLC mode) in terms of dielectiric and voltage holding properties. Research on these switching properties provided us with the technology for switching half-V FLC mode FLCs by using amorphous silicon TFTs.

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