• Journal of Broadcast Engineering
• /
• v.13 no.3
• /
• pp.415-418
• /
• 2008

Some embedded microprocessors do not have an FPU(Floating Point Unit) due to a circuit complexity and power consumption. The performance speed of MPEG-4 AAC decoder on this hardware environment would be slower than corresponding speed for playing back of the decoded results. Therefore, irritating and high-pitched noises are interleaved in the original the audio data. So, in order to play MPEG-4 AAC file on such PDA, a new algorithm that transforms floating-point arithmetic to one with integers, is needed. We have developed a transformation algorithm from floating-point operation to integer operation and implemented the PDA's AAC Player. We also show the efficiency of our proposed method with the experimental results.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.1
• /
• pp.27-34
• /
• 2021

In this paper, we propose a copyright protection scheme for real-time streaming of HEVC(High Efficiency Video Coding) based realistic content. Previous research uses encryption and modular operation for copyright pre-protection and copyright post-protection, which causes delays in ultra high resolution video. The proposed scheme maximizes parallelism by using thread pool based DRM(Digital Rights Management) packaging with only HEVC's CABAC(Context Adaptive Binary Arithmetic Coding) codec and GPU based high-speed bit operation(XOR), thus enabling real-time copyright protection. As a result of comparing this scheme with previous research at three resolutions, PSNR showed an average of 8 times higher performance, and the process speed showed an average of 18 times difference. In addition, as a result of comparing the robustness of the forensic mark, the filter and noise attack, which showed the largest and smallest difference, with a 27-fold difference in recompression attacks, showed an 8-fold difference.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.6
• /
• pp.48-57
• /
• 2003

In this paper, An 8${\times}$l ID-IDCT processor with adder-based distributed arithmetic(DA) and bit-serial method Is presented. To reduce hardware cost and to improve operating speed, the proposed 8${\times}$1 ID-IDCT used the bit-serial method and DA method. The transform of coefficient equation results in reduction in hardware cost and has a regularity in implementation. The sign extension computation method reduces operation clock. As a result of logic synthesis, The gate count of designed 8${\times}$1 1D-IDCT is 17,504. The sign extension processing block has gate count of 3,620. That is 20% of total 8${\times}$1 ID-IDCT architecture. But the sign extension processing block improves more than twice in throughput. The designed IDCT processes 50Mpixels per second and at a clock frequency of 100MHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.1
• /
• pp.55-60
• /
• 2021

This paper relates with the performance evaluation of QE-MMA (Quantized Error-MMA) adaptive equalization algorithm based on the stepsize and quantizer bit number in order to reduce the intersymbol interference due to nonlinear distortion occurred in the time dispersive channel. The QE-MMA was proposed using the power-of-two arithmetic for the H/W implementation easiness substitutes the multiplication and addition into the shift and addition in the tap coefficient updates process that modifies the SE-MMA which use the high-order statistics of transmitted signal and sign of error signal. But it has different adaptive equalization performance by the step size and quantizer bit number for obtain the sign of error in the generation of error signal in QE-MMA, and it was confirmed by computer simulation. As a simulation, it was confirmed that the convergence speed for reaching steady state depend on stepsize and the residual quantities after steady state depend on the quantizer bit number in the QE-MMA adaptive equalization algorithm performance.

• Journal of the Korean Institute of Navigation
• /
• v.18 no.4
• /
• pp.137-146
• /
• 1994

In this paper, a new algorithm to measure the ultrasonic travel time is proposed, which is fundamental to estimate distance depth and volume in several media. Pulse wave has been used to measure travel time of transmitted signal. However, due to the characteristic of transducer and propagation, the received signal is so distorted that it is difficult to measure travel time, which is propagation, the received signal is so distorted that it is difficult to measure travel time, which is to be time difference between transmitted and received signals. In this proposed method, transmitted and received signal are transformed respectively into norm phase newly designed by this paper and displayed on phase-time curve. And travel time is simply determined by the arithmetic numerical mean of time difference at the identical norm phase on the phase-time curves of transmitted and received signals. This method has several features; firstly, travel time is calculated analytically with high accuracy by least square error method, secondly, it is useful to compare the difference of signal magnitude for time information, thirdly, noise and discrete errors are relatively small, finally, the measurement accuracy is not influenced by D.C. bias. In particular, this method is useful and applicable to measuring very short distance and sound speed with high accuracy.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.9C
• /
• pp.861-870
• /
• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.36 no.8
• /
• pp.807-815
• /
• 2008

In this paper, design, development and evaluation of DIP(Database Interface Program) are presented. The main purpose of this study is to improve the simulation quality to get more realistic response of target system. The designed and developed major function is composed of flexible memory structure, efficient arithmetic database language and high speed interpolation/extrapolation algorithm. To evaluate the operation speed and accuracy of returned data, trim simulation is performed based on in-house software and, DIP is applied to existing real-time simulator such as engineering HQS(Handling Quality Simulator) to evaluate reliability and performance. The result of evlaution reveals that calculation speed and data accuracy are satisfied, and flight performance is satisfied in the real-time simulator environments.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4B
• /
• pp.708-714
• /
• 2000

In this paper, an one-dimensional VLSI array for high speed processing of fractal image compression algorithm based the quad-tree partitioning method is proposed. First of all, the single assignment code algorithm is derived from the sequential Fisher's algorithm, and then the data dependence graph(DG) is obtained. The two-dimension array is designed by projecting this DG along the optimal direction and the one-dimensional VLSI array is designed by transforming the obtained two-dimensional array. The number of Input/Output pins in the designed one-dimensional array can be reduced and the architecture of process elements(PEs) can he simplified by sharing the input pins of range and domain blocks and internal arithmetic units of PEs. Also, the utilization of PEs can be increased by reusing PEs for operations to the each block-size. For fractal image compression of 512X512gray-scale image, the proposed array can be processed fastly about 67 times more than sequential algorithm. The operations of the proposed one-dimensional VLSI array are verified by the computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.7
• /
• pp.53-61
• /
• 2004

In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.14 no.4
• /
• pp.123-134
• /
• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.