• 제목/요약/키워드: High-Speed Circuit

검색결과 1,097건 처리시간 0.033초

고속신호처리를 위한 고주파용 Op-Amp 설계 (A High Frequency Op-amp for High Speed Signal Processing)

  • 신건순
    • 한국정보통신학회논문지
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    • 제6권1호
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    • pp.25-29
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    • 2002
  • High speed 신호처리는 통신분야, SC circuit, HDTV, ISDN 등에서 관심이 더욱 승가하고 있으며, high speed 신호처리를 위한 많은 방법들이 있다. 본 논문에서는 CMOS 공정에서 고주파 Op-amp의 실현을 의한 설계를 기술하였다. 아날로그 집적회로를 기초로 하는 high speed op-amp의 기능을 제한하는 요소 중 한가지는 유효 주파수 범위이다. 본 논문에서는 $C_{L}$ =2pF에서 단위이득 주파수가 170MHz인 향상된 대역폭적을 가지는 CMOS op-amp 구조를 계발한다. 공정은 1.2$\mu$디자인 룰을 따른다. 본 논문에서 제시한 CMOS op-amp 고주파 SC filter에서 요구하는 큰 커패시터 부하에서의 넓고 안정된 대역폭을 얻기에 매우 적합하다.

Electromagnetic Actuator with Novel Electric Brake for Circuit Breaker

  • Bae, Byungjun;Kim, Minjae
    • Journal of Magnetics
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    • 제21권3호
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    • pp.340-347
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    • 2016
  • At the stroke end of an electromagnetic circuit breaker, the high speed of the mover makes a huge impact at the contact point, which induces the rebound problem of the mover that causes a breaker failure. Thus, a speed reduction equipment is required to address such problems. This study suggests to use an electric brake reduces the speed at the end of the stroke. The proposed circuit breaker which adopts the electric brake has a variable speed reduction function such that the continued rebound phenomenon ceases to occur. The electric brake is designed by the Finite Element Method (FEM) and the circuit and motion equations are solved using Time Difference Method (TDM). The comparisons between the simulation and experiments demonstrated the usefulness and validity of this study.

초전도 논리연산자의 개발 (Development of Superconductive Arithmetic and Logic Devices)

  • 강준희
    • Progress in Superconductivity
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    • 제6권1호
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    • pp.7-12
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    • 2004
  • Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

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Improved Torque Calculation of High Speed Permanent Magnet Motor with Compressor Loads Using Measured Power Factor Angle and Analytical Circuit Parameters

  • Choi, Jang-Young;Jang, Seok-Myeong;Lee, Sung-Ho
    • Journal of international Conference on Electrical Machines and Systems
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    • 제2권2호
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    • pp.159-164
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    • 2013
  • Difficulty of torque measurements in high-speed permanent magnet (HSPM) motors has necessitated the development of improved torque calculations. Hence, this paper presents an analytical torque calculation of a high speed permanent magnet (HSPM) motor based on the power factor angle. On the basis of analytical magnetic field solutions, the equations for circuit parameters such as back-emf and synchronous inductance are derived analytically. All analytical results are validated extensively by non-linear finite element (FE) calculations and measurements. The internal angle (${\delta}$) between the back-emf and the phase current is calculated according to the rotor speed by using analytical circuit parameters and the measured power factor because this angle is not measured but estimated in case of sensorless drive of the HSPM motor, significantly affecting torque calculation. Finally, the validity of the torque analysis method proposed in this paper is confirmed, by showing that the torque calculated on the basis of the internal angle is in better agreement with the measurements.

신뢰성 평가를 위한 LV 회로 분석시뮬레이터 구현에 관한 연구 (A Study on Implementation of LV circuit analysis simulator for Reliability Evaluation)

  • 장영건;조경환;박계서;최권희
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2000년도 추계학술대회 논문집
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    • pp.602-609
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    • 2000
  • This study is concerned with analysis and reliability evaluation of LV circuit in Cab Cubicle system which controls train to keep safety in High Speed Train. LV circuit is operated with diagnosis system as safety system. In this paper, we suggest a design and an implementation method to analyze LV circuit or trace fault area in LV circuit. This simulator uses 28 package modules and examines input and output by equations. So, user can trace where is fault area. The implemented system can be expected to be useful for long term test and evaluation of circuit in high speed train systems. We expect reduction to diagnosis area or repair time by this simulator.

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동적모델에 기반한 고압회로차단기의 설계 및 해석 (Design and Analysis of Power Circuit Breaker Mechanism Based on the Dynamic Model)

  • 권병희;안길영;오일성;서정민;김수현
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2001년도 춘계학술대회논문집B
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    • pp.476-481
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    • 2001
  • In this paper, based on the developed dynamic model of a vacuum circuit breaker mechanism, the development of the new circuit breaker with less energy mechanism is focused. The energy flow analysis of the original mechanism is carried out to show where the elastic potential energies of pre-loaded springs are transmitted. Through energy flow analysis, the concept design of the new circuit breaker with less energy mechanism is proposed, and then the detailed design is carried out through the design process based on the verified dynamic model. Comparing simulation results with experiment using a high-speed camera, the appropriateness of the proposed design procedures for the rapid circuit breaker mechanism is shown.

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감마선용 고속 피크홀드회로의 개발 (Development of High Speed Peak-hold Circuit for Gamma-ray)

  • 최기성;최규식
    • 한국항행학회논문지
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    • 제20권6호
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    • pp.612-616
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    • 2016
  • 감마선이 존재하는 시설물에서는 발생 즉시 이를 발견하여 처리해야 하며 이와 관련하여 무작위적으로 발생하는 신호를 처리하는 소프트웨어적인 방법을 사용하기도 하나 소프트웨어의 메모리 용량과 처리시간이 커지게 된다. 한편 하드웨어적인 방법으로 신호처리할 수 있는 회로가 일반화되어 있으나 발생 신호의 크기가 미약하고 속도가 고속인 경우에는 이에 대응하지 못한다. 하드웨어적으로 효과적으로 신호처리하려면 값이 매우 비싼 부품과 복잡한 회로를 필요로 한다. 따라서 본 연구에서는 크기는 미약하지만 속도가 고속인 감마선 발생신호에 대해서 하드웨어적으로 간단한 피크홀드 회로를 개발하여 피크 시점에서 ADC가 신호값을 직접 읽어냄으로써 감마선 신호의 피크치를 검출하는 회로를 연구, 개발하였다. 이러한 방법으로 하면 복잡한 소프트웨어 신호처리 방법을 사용하지 않고도 고속 발생신호를 효과적으로 포착할 수 있으므로 감마선의 존재가 농후한 방사능 환경에서 이를 사용하기에 적합하다.

빠른 전하 균일화를 위한 새로운 구조의 셀 밸런싱 회로 (A Novel Cell Balancing Circuit for Fast Charge Equalization)

  • 박동진;최시영;김용욱;김래영
    • 전력전자학회논문지
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    • 제20권2호
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    • pp.160-166
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    • 2015
  • This study proposes an improved cell balancing circuit for fast equalization among lithium-ion (Li-ion) batteries. A simple voltage sensorless charge balancing circuit has been proposed in the past. This cell balancing circuit automatically transfers energy from high-to low-voltage battery cells. However, the circuit requires a switch with low on-resistance because the balancing speed is limited by the on-resistance of the switch. Balancing speed decreases as the voltage difference among the battery cells decrease. In this study, the balancing speed of the cell balancing circuit is enhanced by using the auxiliary circuit, which boosts the balancing current. The charging current is determined by the nominal battery cell voltage and thus, the balancing speed is almost constant despite the very small voltage differences among the batteries. Simulation results are provided to verify the validity of the proposed cell balancing circuit.

A Low-Noise and Small-Size DC Reference Circuit for High Speed CMOS A/D Converters

  • Hwang, Sang-Hoon;Song, Min-Kyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제7권1호
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    • pp.43-50
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    • 2007
  • In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.

스프링구동 링크를 가진 기중 회로차단기의 동적 분석 (Dynamic Analysis of Air Circuit Breaker with Spring-Actuated Linkage)

  • 안길영;권병희;오일성;윤영관;최종웅
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.812-815
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    • 1997
  • A dynamic model of air circuit breaker with a spring-actuated linkage is derived, and its validation for analysis and design, particularly appropriateness for an analysis of high-speed motion behavior are checked through experiments. The dynamic model is developed through the modeling process based on ADAMS and Pro/Engineer. The simulation results of derived dynamic models for the rapid closing and opening operations are compared with actual responses using a high-speed camera and investigated to validate their usefulness.

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