• Title/Summary/Keyword: High voltage gain

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A Radio-Frequency PLL Using a High-Speed VCO with an Improved Negative Skewed Delay Scheme (향상된 부 스큐 고속 VCO를 이용한 초고주파 PLL)

  • Kim, Sung-Ha;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.42 no.6
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    • pp.23-36
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    • 2005
  • PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.

A Wafer Level Packaged Limiting Amplifier for 10Gbps Optical Transmission System

  • Ju, Chul-Won;Min, Byoung-Gue;Kim, Seong-Il;Lee, Kyung-Ho;Lee, Jong-Min;Kang, Young-Il
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.189-195
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    • 2004
  • A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

A Design of Transceiver for 13.56MHz RFID Reader using the Peak Detector with Automatic Reference Voltage Generator (자동 기준전압 생성 피크 검출기를 이용한 13.56 MHz RFID 리더기용 송수신기 설계)

  • Kim, Ju-Seong;Min, Kyung-Jik;Nam, Chul;Hurh, Djyoung;Lee, Kang-Yun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.3
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    • pp.28-34
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    • 2010
  • In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.

The Design of K-band Up converter with the Excellent IMD3 Performance (3차 혼변조 왜곡 특성이 우수한 K-band 상향변환기 설계)

  • 정인기;이영철
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.5
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    • pp.1120-1128
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    • 2004
  • In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

Design of Compact Stepped Open Slot Antenna for UWB Applications (UWB 응용을 위한 소형 계단형 개방 슬롯 안테나 설계)

  • Yeo, Junho;Lee, Jong-Ig
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.1
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    • pp.1-7
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    • 2017
  • In this paper, a design method for a compact stepped open slot antenna for an operation in the UWB band is studied. The proposed antenna is miniaturized by inserting L-shaped slots on the ground plane of the stepped open slot antenna through the creation of a resonance in the low frequency, and a strip director is appended to the antenna in order to increase the gain in the middle and high frequency regions. The effects of varying the length of the L-shaped slots, the distance between the director and the slot antenna, and the director length on input reflection coefficient and realized gain characteristics of the proposed antenna are analyzed. The optimized antenna with the size of $30mm{\times}30mm$ is fabricated on an FR4 substrate, and the experiment results show that the antenna has a frequency band of 3.02-11.04 GHz for a VSWR < 2, which assures the operation in the UWB band.

Design of Frequency Reconfigurable Antenna with the Vertically Stacked Dipole Structure (수직 적층형 다이폴 구조를 갖는 주파수 재구성 안테나 설계)

  • Jung, Young-Jin;Hong, Ic-Pyo;Eom, Soon-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.5
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    • pp.552-559
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    • 2011
  • In this paper, the frequency reconfigurable antenna is proposed and designed. The proposed antenna is designed using the vertically stacked dipole structures and have the operating band for Cellular, PCS/WCDMA/Wibro/WiFi and WiMAX. The operating frequency band is selected by three pair of PIN diodes using the voltage difference between each dipole antenna and feeding transmission lines. The proposed antenna meets the required operating bandwidth and the maximum gain for each frequency band are measured as 6.3 dBi, 5.4 dBi and 5.8 dBi, respectively. The proposed antenna in this paper can be applied for the future mobile small base station or repeater antenna because this antenna can provide the small size and high gain features.

Design of Two-Stage X-Band Power Amplifier Using GaN-HEMT (GaN-HEMT를 이용한 X-대역 이단 전력증폭기 설계)

  • Lee, Wooseok;Lee, Hwiseob;Park, Seungkuk;Lim, Wonseob;Han, Jaekyoung;Park, Kwanggun;Yang, Youngoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.1
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    • pp.20-26
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    • 2016
  • This paper presents an X-band two-stage power amplifier using GaN-HEMT. Two-stage structure was adopted to take its high gain and simple inter-stage matching network. Based on a 3D EM simulation, the bond-wire inductance and the parasitic capacitance were predicted. By reducing bond-wire inductance, Q of the matching network is decreased and the bandwidth is improved. The implemented two-stage PA shows a power gain of more than 16 dB, saturated output power of more than 42.5 dBm, and a efficiency of more than 35 % in frequency range of 8.1~8.5 GHz with an operating voltage of 40 V.

Design of a CPW-fed Double-Dipole Quasi-Yagi Antenna (CPW 급전 이중 다이폴 준-야기 안테나 설계)

  • Yeo, Junho;Lee, Jong-Ig
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.11
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    • pp.1518-1523
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    • 2018
  • A method for designing a DDQYA fed by a CPW is proposed in this paper. The proposed CPW-fed DDQYA consists of two series-connected strip dipoles, a ground reflector, and a strip-pair director. Instead of the conventional microstrip feed line in which the signal line is located on the substrate opposite to the antenna, a CPW is used because CPW is located on the same side with the antenna, and so the fabrication is easy. The strip-pair director is composed of two horizontally-separated strips, and it is added above the second dipole to enhance the gain in the high frequency region. A prototype of the proposed CPW-fed DDQYA is fabricated on an FR4 substrate. The fabricated antenna has a frequency band of 1.66-3.38 GHz(68.3%) for a voltage standing wave ratio < 2, and measured gain ranges 5.0-7.3 dBi over a frequency band of 1.60-2.90 GHz.

Miniaturization of Open Stepped Slot Antenna (계단형 개방 슬롯 안테나의 소형화)

  • Yeo, Junho;Lee, Jong-Ig
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.61-62
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    • 2016
  • In this paper, a design method for a compact stepped open slot antenna for an operation in the UWB band is studied. The proposed antenna is miniaturized by inserting L-shaped slots on the ground plane of the stepped open slot antenna through the creation of a resonance in the low frequency, and a strip director is appended to the antenna in order to increase the gain in the middle and high frequency regions. The effects of varying the length of the L-shaped slots, the distance between the director and the slot antenna, and the director length on input reflection coefficient and realized gain characteristics of the proposed antenna are analyzed. The optimized antenna with the size of $30mm{\times}30mm$ is fabricated on an FR4 substrate, and the experiment results show that the antenna has a frequency band of 3.02-11.04 GHz for a VSWR < 2, which assures the operation in the UWB band.

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A Study on the Ultra Small Size 25 Watt High Power Amplifier for Satellite Mobile Communications System at L-Band (L-band 위성통신 시스템을 위한 극소형 25 Watt 고출력증폭기에 관한 연구)

  • Jeon, Joong-Sung;Ye, Byeong-Duck;Kim, Dong-Il
    • Journal of Navigation and Port Research
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    • v.26 no.1
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    • pp.22-27
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    • 2002
  • The 25 Watt hybrid MIC SSPA has been developed in the frequency rang from 1.6265 GHz to 1.6465 GHz for uplink of INMARST's earth station. To simplify the fabrication process, the whole system is designed of two parts composed of a friving amplifier and a power amplifier. The Motorolas MRF-6401 is used for driving part, the Motorolas MRF-16006 and MRF-16030 is used the power amplifier. We reduced weight and volume of high power amplifier through arranging the bias circuits in the same housing. The realized SSPA has more than 30 dB for gain within 20 MHz bandwidth, and the voltage standing wave ratios(VSWR) of input and output port are less than 1.7, respectively. The output power of 44 dBm is achieved at the 1 dB gain compression point of 106365 GHz These results reveal a high power amplifier of 25 Watt which is the design target. The Proposed SSPA manufacture techniques in this paper can be applied to the implementation of high power amplifiers for some radars and SCPC.