• Journal of Electrical Engineering and Technology
• /
• v.13 no.5
• /
• pp.1886-1900
• /
• 2018

This paper proposes a confronting feedback control structure and controllers for positive output elementary super lift Luo converters (POESLLCs) working in discontinuous conduction mode (DCM). The POESLLC offers the merits like high voltage transfer gain, good efficiency, and minimized coil current and capacitor voltage ripples. The POESLLC working in DCM holds the value of not having right half pole zero (RHPZ) in their control to output transfer function unlike continuous conduction mode (CCM). Also the DCM bestows superlative dynamic response, eliminates the reverse recovery troubles of diode and retains the stability. The proposed control structure involves two controllers respectively to control the voltage (outer) loop and the current (inner) loop to confront the time-varying ON/OFF characteristics of variable structured systems (VSSs) like POESLLC. This study involves two different combination of feedback controllers viz. the proportional integral controller (PIC) plus sliding mode controller (SMC) and the fuzzy logic controller (FLC) plus SMC. The state space averaging modeling of POESLLC in DCM is reviewed first, then design of PIC, FLC and SMC are detailed. The performance of developed controller combinations is studied at different working states of the POESLLC system by MATLAB-Simulink implementation. Further the experimental corroboration is done through implementation of the developed controllers in PIC 16F877A processor. The prototype uses IRF250 MOSFET, IR2110 driver and UF5408 diodes. The results reassured the proficiency of designed FLC plus SMC combination over its counterpart PIC plus SMC.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.9
• /
• pp.6247-6253
• /
• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.12
• /
• pp.242-246
• /
• 2012

This paper presents an integrated low noise and highly linear wideband RF front-end for a digital terrestrial and cable TV tuner, which are used as a part of double-conversion TV tuner. The low noise amplifier (LNA) has a low noise figure and high linearity by adopting a noise canceling technique based on current amplification. The up-conversion mixer and SAW buffer have high linearity by employing a third order intermodulation cancellation technique. The proposed RF front-end is designed in a $0.18{\mu}m$ CMOS and draws 60 mA from a 1.8 V supply voltage. The RF front-end shows a voltage gain of 30 dB, an average single side-band noise figure of 4.2 dB, an IIP2 of 40 dBm, and an IIP3 of -4.5 dBm for the entire band from 48 MHz to 862Hz.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.479-479
• /
• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• BioChip Journal
• /
• v.12 no.4
• /
• pp.332-339
• /
• 2018

The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to $80{\mu}V$ while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of $2{\mu}W$ under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves $60G{\Omega}$ of input impedance and input referred noise of $8.5nv/{\sqrt{Hz}}$ over the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists.

• Journal of Biomedical Engineering Research
• /
• v.20 no.2
• /
• pp.205-212
• /
• 1999

When we want to observe and record a patient's EEG in an operating room, the operation of electrosurgical unit(ESU) causes undesirable artifacts with high frequency and high voltage. These artifacts make the amplifiers of the conventional EEG system saturated and prevent the system from measuring the EEG signal. This paper describes a high-performance bipolar EEG amplifier for a CSA (compressed spectral array ) system with reduced ESU artifacts. The designed EEG amplifier uses a balanced filter to reduce the ESU artifacts, and isolates the power supply and the signal source of the preamplifier from the ground to cut off the current from the ESU to the amplifier ground. To cancel the common mode noise in high frequency, a high CMRR(common mode rejection ratio) diffferential amplifier is used. Since the developed bipolar EEG amplifier shows high gain, low noise, high CMRR, high input impedance, and low thermal drift, it is possible to observe and record more clean EEG signals in spite of ESU operation. Therefore the amplifier may be applicable to a high-fidelity CSA system.

• Journal of electromagnetic engineering and science
• /
• v.1 no.1
• /
• pp.73-77
• /
• 2001

We studied the fabrication of GaAs-based pseudomorphic high electron mobility transistors(PHEMT`s) for the purpose of millimeter- wave applications. To fabricate the high performance GaAs-based PHEMT`s, we performed the simulation to analyze the designed epitaxial-structures. Each unit processes, such as 0.1 m$\mu$$\Gamma$-gate lithography, silicon nitride passivation and air-bridge process were developed to achieve high performance device characteristics. The DC characteristics of the PHEMT`s were measured at a 70 $\mu$m unit gate width of 2 gate fingers, and showed a good pinch-off property ($V_p$= -1.75 V) and a drain-source saturation current density ($I_{dss}$) of 450 mA/mm. Maximum extrinsic transconductance $(g_m)$ was 363.6 mS/mm at $V_{gs}$ = -0.7 V, $V_{ds}$ = 1.5 V, and $I_{ds}$ =0.5 $I_{dss}$. The RF measurements were performed in the frequency range of 1.0~50 GHz. For this measurement, the drain and gate voltage were 1.5 V and -0.7 V, respectively. At 50 GHz, 9.2 dB of maximum stable gain (MSG) and 3.2 dB of $S_{21}$ gain were obtained, respectively. A current gain cut-off frequency $(f_T)$ of 106 GHz and a maximum frequency of oscillation $(f_{max})$ of 160 GHz were achieved from the fabricated PHEMT\\`s of 0.1 m$\mu$ gate length.h.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.4
• /
• pp.394-402
• /
• 2013

This paper presents design, fabrication and ruggedness test of switching-mode power amplifier using GaN(Gallium Nitride) HEMT(High Electron Mobility Transistor) for S-band radar applications. The power amplifier is designed to Class-F for high efficiency. The input signal for the measurement of the power amplifier is pulse signal at $100{\mu}s$ pulse width and duty cycle of 10 %. The measurement results of the fabricated Class-F power amplifier are a power gain of 10.8 dB, an output power of 40.8 dBm, a power added efficiency(PAE) of 54.2 %, and a drain efficiency of 62.6 %, at the center frequency. We proposed reliability test set-up of a power amplifier for ruggedness test. And we measured output power and efficiency according to VSWR(Voltage Standing Wave Ratio) variation. The designed power amplifier achieved output power of 32.6~41.1 dBm and drain efficiency of 23.4~63 % by changing VSWR, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.05a
• /
• pp.415-419
• /
• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• Journal of Power Electronics
• /
• v.18 no.2
• /
• pp.332-342
• /
• 2018

This paper proposes a parameter design method for multi-element resonant converters (MERCs) with a unique resonant zero point (RZP). This method is mainly composed of four steps. These steps include program filtration, loss comparison, 3D figure fine-tuning and priority compromise. It features easy implementation, effectiveness and universal applicability for almost all of the existing RZP-MERCs. Meanwhile, other design methods are always exclusive for a specific topology. In addition, a novel dual-CTL converter is also proposed here. It belongs to the RZP-MERC family and is designed in detail to explain the process of parameter selection. The performance of the proposed method is verified experimentally on a 500W prototype. The obtained results indicate that with the selected parameters, an extensive dc voltage gain is obtained. It also possesses over-current protection and minimal switching loss. The designed converter achieves high efficiencies among wide load ranges, and the peak efficiency reaches 96.9%.