• International Journal of Advanced Culture Technology
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• v.10 no.3
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• pp.332-338
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• 2022

The article presents a concept of designing a Multiplexer circuit which acts as a "Selector" and that becomes capable to select different speed created at different TTL Gate configurations; Standard TTL(Normal Speed), High Speed TTL(High Speed), Schottky TTL(Super High Speed) and further connect the selected Gate speed to the CAR shape created using C-Programming at Computer Graphics and finally CAR shape display at different speed to the color TV. The Multiplexer supporting efficient and more reliable selection criteria using "Logical based selection criteria" and further the output from multiplexer is provided to CAR shape created using c-programming and finally CAR shape is display to color TV system. Basic purposes and assumptions regarding the design and development of this system as well as a description of its operation have been presented.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.25-37
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• 1996

To process computer graphics in real time, the high-speed operations(multiplier and adder) are needed to increase the speed of graphic process. RNS(Residue Number System) is integer number system that has the parallel and high-speed operation. Also, it is able to design both high-speed multiplier and adder, since a cyclic group has an isomorphic relation between multiplication and addition in RNS. So in this paper, DRNS(Double Residue Number System) is proposed, it is used for the multiplier and the adder, which are designed using a circulative code for the high-speed graphic processor in RNS. The designed multiplier would operate with the speed of 87Mzz two TTL using 74s09 and 74s32.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.167-173
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• 2005

The isolation of the series PIN diode switch is restricted by the parallel capacitance of PIN diode and the switch driver circuit limits switching speed of PIN diode switch. To overcome these problems, a high isolation and high switching speed Pin diode switch is proposed adapting the parallel resonant inductance and TTL compatible switch driver circuit. The measurement results of the 3 GHz PM diode switch show 1 GHz frequency band, less than 1.5 dB insertion loss, 65 dB isolation, more than 15 dB return loss and less than 30 ns switching speed. In particular the 3 GHz PIN diode switch using the parallel resonant inductance exhibits the improvement of isolation by 15 dB.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.16-25
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• 1997

This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1A
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• pp.47-53
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• 2003

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7${\mu}m$ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.51-58
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• 2002

In this paper, a 155/311 Mb/s MUX/DEMUX chip using ECL macrocell away has been developed with a single device. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s(or 311 Mb/s) serial data output, and is to interleave a serial input bit stream of 155 Mb/s(or 311 Mb/s) into the parallel output of 51 Mb/s. The input and output of the device ate TTL compatible at the low-speed end, but 100k ECL compatible at the high-speed end. The device has been fabricated with Motorola ETL3200 macrocell away The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 220ps at the high-speed end.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.345-348
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• 2000

In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.2
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• pp.47-54
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• 1982

In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.364-371
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• 2007

In this paper, the design and implementation of high-power PIN diode switch modules and high-speed switch driver circuits are presented for Wibro base stations. To prevent isolation degradation due to parasitic inductances of conventional packaged PIN diodes and to improve power handling capabilities of the switch modules, bare diode chips are used and carefully placed in a PCB layout, which makes bonding wire inductances to be absorbed in the impedance of a transmission line. The switch module is designed and implemented to have a maximum performance while using a minimum number of the diodes. It shows an insertion loss of ${\sim}0.84\;dB$ and isolation of 80 dB or more at 2.35 GHz. The switch driver circuit is also fabricated and measured to have a switching speed of ${\sim}200\;nsec$. The power handling capability test demonstrates that the module operates normally even under a digitally modulated 70 W RF signal stress.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2116-2118
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• 2000

In the technique of Q-switching, very fast electronically controlled optical shutters can be made by using the electro-optic effect in crystals or liquids. The driver for the Pockels cell must be a high-speed, high-voltage switch which also must deliver a sizeable current. Common switching techniques include the use of vacuum tubes, cold cathode tubes, thyratrons, SCRs, and avalanche transistors. Semiconductor devices such as SCRs, avalanche transistors, and MOSFETs have been successfully employed to drive Pockels cell Q-switch. In this study, a simple driver for the Pockels cell Q-switch was developed by using SCRs, pulse transformer and TTL ICs. The Pockels cell Q-switch which was operated by this driver was employed in pulsed Nd:YAG laser system to investigate the operating characteristics of this Q-switch. And we have investigated the output characteristics of this Q-switch as a function of the Q-switch delay time to Xe flashlamp current on.