• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.166-176
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• 1995

This paper presents a new high-level synthesizer for ASIC designs using ASIC library or FPGAs. DAMUL defines the VHDL description for a specified hardware and allocate some VHDL codes, which describe the behavioral specification, to the corresponding hardware before the synthesis. The interconnections are implemented by the multiplexers, and the objective of allocation is the minimization of the number of multiplexers. Also, the dedicated registers is used for global variables, in order to implement the other necessary registers as well as status and control registers. The effectiveness of the proposed system is shown by the synthesis results of benchmark circuits.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.453-454
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• 2008

Modern VLSI designs get increasingly complex and time-to-market constraints get tighter. Using high level languages is one of the most promising solutions for improving design productivity by raising the level of abstraction. In high level synthesis process, most important step is scheduling. In this paper, we propose fast and efficient scheduling method under timing constraint based on list scheduling. Experimental results on well known data path intensive designs show fast execution times (less than 0.5 sec) and similar results when compared to optimal solutions [1].

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1021-1024
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• 1998

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.819-822
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• 1998

The high complexity of digital circuits has changed the digital circuits design mehtods from schemeatic-based to hardware description languages like VHDL, verilog that make hardware faults become more hard to detect. Thus test generation to detect hardware defects is very important part of the design. But most of the test generation methods are gate-level based. In this paper new high-level test generation method to detect stuck-at-faults on gate level is described. This test generation method is independent of synthesis results and reduce the time and efforts for test generation.

• Asian-Australasian Journal of Animal Sciences
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• v.11 no.6
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• pp.713-717
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• 1998

The synergistic effect of fetal calf serum (FCS) and chicken embryo extract (CEE) on protein synthesis of chicken embryo myoblasts was examined. Myoblasts were derived from chicken embryo cultured for 14 days by trypsin digestion and cultured in 5% $CO^2/95%$ air at $37^{\circ}C$. When myoblasts were cultured at the low level of cell density (20-50% of well), CEE enhanced the ability of FCS to stimulate protein synthesis of myoblasts. However, there was no significant effect of CEE to stimulate protein synthesis of myoblasts cultured at high level of cell density (100% of well).

• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.1-8
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• 2023

This paper presents the design and implementation of Crystals-Kyber, a next-generation postquantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the Crystals-Kyber algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU106 FPGA. Finally, the video was recorded and H.264 compressed with Python code in the PYNQ framework, and the video encryption and decryption were accelerated using Crystals-Kyber hardware accelerator implemented on the FPGA.

• Advances in aircraft and spacecraft science
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• v.5 no.2
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• pp.177-186
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• 2018

This paper deals with the idea to replace the usual high-level sine sweep test on shaker at system level, very severe, by a low level one completed by a transient test in the same configuration, in order to be more representative of the real environment, thus limiting over testing and improving the payload comfort. The problem of the transient test specification is first discussed. The proposed solution is to derive from LV/SC coupled analyses a shock response spectrum corresponding to two damping ratios. Then, the question of adequate shock synthesis is tackled. A new method with a given spectrum is considered for better potential and accuracy than the usual wavelets. A campaign on the Intespace bi-shaker devoted to system level showed its capability to perform the resulting test with one spectrum. First investigations to extend this approach to two spectra are in progress.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.116-124
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• 1994

This paper describes the design of a high-level synthesis system. ISyn: Interface Synthesis System for ISPS-A. which generates hardware satisfying timing constraints. The original version of ISPS is extended to be used for the description/capture of interface operations and timing constraints in the ISPS-A. To generate the schedule satisfying interface constraints the scheduling process is divided into two steps:pre-scheduling and post-scheduling. ISyn allocates hardware modules with I/O ports by the clique partitioning algorithm. Experimental results show that ISyn is capable of synthesizing hardware modules effectively for internal and/or interactive operations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.24-31
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• 1998

This paper presents a pipeline high-level synthesis tool for designing trace-back systolic array viterbi decoder. It consists of a dta flow graph(DFG) generator and a pipeline data path synthesis tool. First, the DFG of the vitrebi decoder is generated in the from of VHDL netlist. The inputs to the DFG generator are parameters of the convolution encoder. Next, the pipeline scheduling and allocationare performed. The synthesis tool explores the design space efficiently, synthesizes various designs which meet the given constraints, and choose the best one.

• Journal of Microbiology and Biotechnology
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• v.27 no.7
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• pp.1345-1358
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• 2017

The impact of overproduction of a heterologous protein on the metabolic system of host Lactococcus lactis was investigated. The protein expression profiles of L. lactis IL1403 containing two near-identical plasmids that expressed high- and low-level of the green fluorescent protein (GFP) were examined via shotgun proteomics. Analysis of the two strains via high-throughput LC-MS/MS proteomics identified the expression of 294 proteins. The relative amount of each protein in the proteome of both strains was determined by label-free quantification using the spectral counting method. Although expression level of most proteins were similar, several significant alterations in metabolic network were identified in the high GFP-producing strain. These changes include alterations in the pyruvate fermentation pathway, oxidative pentose phosphate pathway, and de novo synthesis pathway for pyrimidine RNA. Expression of enzymes for the synthesis of dTDP-rhamnose and N-acetylglucosamine from glucose was suppressed in the high GFP strain. In addition, enzymes involved in the amino acid synthesis or interconversion pathway were downregulated. The most noticeable changes in the high GFP-producing strain were a 3.4-fold increase in the expression of stress response and chaperone proteins and increase of caseinolytic peptidase family proteins. Characterization of these host expression changes witnessed during overexpression of GFP was might suggested the metabolic requirements and networks that may limit protein expression, and will aid in the future development of lactococcal hosts to produce more heterologous protein.