• Journal of the Korean institute of surface engineering
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• v.36 no.4
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• pp.334-338
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• 2003

$BCl_3$고밀도 평판형 유도결합 플라즈마(High Density Planar Inductively Coupled Plasma)를 이용하여 AlGaAs와 InGaP의 건식식각에 대하여 연구하였다. 본 실험에서는 ICP 소스파워(0∼500 W), RIE 척 파워(0-150 W), 공정압력(5∼15 mTorr)의 변화에 따른 AlGaAs와 InGaP의 식각률, 식각단면 그리고 표면 거칠기 등을 분석 하였다. 또, 공정 중 OES(Optical Emission Spectroscopy)를 이용하여 in-situ로 플라즈마를 관찰하였다. $BCl_3$ 유도결합 플라즈마를 이용한 AlGaAs의 식각결과는 우수한 수직측벽도와(>87$^{\circ}$) 깨끗하고 평탄한 표면(RMS roughness = 0.57 nm)을 얻을 수 있었다. 반면, InGaP의 경우에는 식각 후 표면이 다소 거칠어진 것을 확인할 수 있었다. 모든 공정조건에서 AlGaAs의 식각률이 InGaP보다 더 높았다. 이는 $BCl_3$ 유도결합 플라즈마를 이용하여 InGaP을 식각하는 동안 $InCl_{x}$ 라는 휘발성이 낮은 식각부산물이 형성되어 나타난 결과이다. ICP 소스파워와 RIE 척파워가 증가하면 AlGaAs와 InGaP모두 식각률이 증가하였지만, 공정압력의 증가는 식각률의 감소를 가져왔다. 그리고 OES peak세기는 공정압력과 ICP 소스파워의 변화에 따라서는 크게 변화하였지만 RIE 척파워에 따라서는 거의 영향을 받지 않았다.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1382-1383
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• 2006

ZnO 박막은 wide band gap(Eg=3.37eV)의 derect band gap을 갖고 있기 때문에 여러 소자로의 응용가능성에 큰 기대를 하고 있는 물질이다. 본 논문에서는 소자 제조과정에서 요구되는 ZnO 박막의 식각변수에 따른 식각율과 식각특성에 관하여 연구하였으며 Inductively coupled plasma(ICP)를 사용하여 $BCl_3$/Ar 가스를 혼합하여 식각을 하였다. $BCl_3$/Ar=8/2 플라즈마에서 화학적 식각의 도움을 받아 ZnO 박막의 식각률은 1724 ${\AA}/min$ 로 최고를 보였으며 이때의 공정 조건은 800 W 의 RF power, 400 W 의 bias power, 1 Pa 의 공정 압력이었다. 식각시에 플라즈마 내부의 이온 거동상태를 측정하기위해 quadrupolemass spectrometer(QMS)를 사용하여 분석하였고 식각후 ZnO 박막의 식각률은 surface profiler(KLA fencer, ${\alpha}$-step 500)을 이용하여 측정하고 ZnO 박막과 B, Cl 라디칼과의 표면 반응 상태를 고찰하기 위하여 식각된 ZnO 박막의 표면을 X-ray photoelectron spectroscopy(XPS)로 분석하였다. XPS를 통하여 ZnO 박막과 Cl 라디칼과 반응을 하여 식각된다는 것과 낮은 휘발성으로 인하여 Ar 이온에 의한 스퍼터링 효과의 도움에 의해서 식각이 진행됨을 확인하였다.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.39-43
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• 2005

In the study, in order to deposit TaN thin film for diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristics of TaN thin films grown PAALD method. Plasma Assisted ALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamino) tantalum) precursor and NH3 reaction gas is shown that TaN thin film deposited high density and amorphous phase with XRD measurement. The degree of diffusion and reaction taking place in Cu/TaN (deposited using 150W PAALD)/$SiO_{2}$/Si systems with increasing annealing temperature was estimated for MOS capacitor property and the $SiO_{2}$, (600${\AA}$)/Si system surface analysis by C-V measurement and secondary ion material spectrometer (SIMS) after Cu/TaN/$SiO_{2}$ (400 ${\AA}$) layer etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to 500$^{\circ}C$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1993-1998
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• 2011

Semiconductor industry needs to have fine patterns in order to fabricate the high density integrated circuit. For nano-scale patterns, hard-mask is used to multi-layer structure which is formed by CVD (chemical vaporized deposition) process. In this work, we prepared single-layer hard-mask by using organic-inorganic hybrid polymer for spin-on process. The inorganic part of hard-mask was much easier etching than photo resist layer. Beside, the organic part of hard-mask was much harder etching than substrate layer. We characterized the optical and morphological properties to the hard mask films using organic-inorganic hybrid polymer, and then etch rate of photo resist layer and hard-mask film were compared. The hybrid polymer prepared from organic and inorganic materials was found to be useful hard-mask film to form the nano-patterns.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.139-145
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• 2005

In the study, in order to deposit TaN thin film using diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristic of TaN thin films deposited PAALD method, PAALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamlno) tantalum) Precursor and $NH_3$ reaction gas is aware that TaN thin film deposited of high density and amorphous phase with XRD measurement The degree of diffusion and react ion taking place in Cu/TaN(deposited using 150 W PAALD)/$SiO_2$/Si systems with increasing annealing temperature was estimated from MOS capacitor property and the $SiO_2(600\;\AA)$/Si system surface analysis by C-V measurement and secondary ion material spectrometer(SIMS) after Cu/TaN/$SiO_2(400\;\AA)$ system etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to $500^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.158-159
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• 2007

반도체 소자의 공정에 있어서 device scaling으로 인한 게이트 산화막 대체 유전체 (high-k)의 공정 개발 확보 방안 필요하다. 본 논문에서는 $Cl_2$/Ar 유도 결합 플라즈마를 이용하여 $HfO_2$ 박막을 식각하였다. $Cl_2$(80 %)/Ar(20 %)의 가스비, 600 W의 RF 전력, -150 V의 직류 바이어스 전압, 20 sccm의 총 가스유랑, 15 mTorr의 압력에서 15.4 nm/min의 최대 식각률을 얻을 수 있었다. 식각 된 $HfO_2$ 박막 표면을 XPS 분석한 결과 Hf와 O는 Cl 라디칼과 반응을 하여 높은 휘발성을 보이지만 Hf-O의 안정된 결합으로 인하여 이온에 의한 스퍼터링 효과에 의해서 식각된다.

• Journal of the Korean Vacuum Society
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• v.7 no.4
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• pp.397-402
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• 1998

$SiO_2$ etch characteristics were studied as a function of the basic parameters, such as the main RF power and the operating pressure in a helicon plasma. $SiO_2$ etch characteristics were improved as the main RF power was increased and the operating pressure was decreased. $SiO_2$ etch selectivity over silicon increased from 2.9 to 25.33 when the RF input power increased from 300 W to 2 kW and from 2.3 to 16.21 when the operating pressure decreased from 10 mTorr to 1.5 mTorr with $C_4F_8$ plasma. We used a quadrupole mass spectrometer to measure the relative abundancies of various ionic and radical species to explain the experimental results and found that when the operating pressure is low and the RF input power is high, the highly selective $SiO_2$ etch is achieved as a result of density increment of the densities of various ionic species.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.213-216
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• 2001

Etching behaviors of ferroelectric $YMnO_3$ thin films were studied by an inductively coupled plasma (ICP). Etch characteristic on ferroelectric $YMnO_3$ thin film have been investigated in terms of etch rate, selectivity and etch profile. The maximum etch rate of $YMnO_3$ thin film is $300{\AA}/min$ at $Ar/Cl_2$ of 2/8, RF power of 800W, dc bias voltage of 200V, chamber pressure of 15mTorr and substrate temperature of $30^{\circ}C$. Addition of $CF_4$ gas decrease the etch rate of $YMnO_3$ thin film. From the results of XPS analysis, YFx compounds were found on the surface of $YMnO_3$ thin film which is etched in $Ar/Cl/CF_{4}$ plasma. The etch profile of $YMnO_3$ film is improved by addition of $CF_4$ gas into the $Ar/Cl_2$ plasma. These results suggest that fluoride yttrium acts as a sidewall passivants which reduce the sticking coefficient of chlorine on $YMnO_3$.

• Applied Chemistry for Engineering
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• v.9 no.7
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• pp.990-997
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• 1998

In this work, the $SiO_2$ films on the silicon substrate with different orientations were first prepared by the low temperature process using the ECR plasma diffusion as a function of microwave power and oxidation time. Before and after thermal treatment, the surface morphology, Si/O ratio from physicochemical properties, and the electrical properties of the oxide films were also investigated. The oxidation rate increased with microwave power, while surface morphology showed the nonuniform due to etching. The film quality, therefore, was lowered with increasing the defect by etching and the content of positive oxide ions in the oxide films from bulk by higher self-DC bias. The content of positive oxide ions in the oxide films with different Si orientations showed Si(100) < Si(111) < poly Si. The defects in $Si/SiO_2$ interface of $SiO_2$ film could be decreased by annealing, while $Q_{it}$ and $Q_f$ were independent of thermal treatment and the dependent on concentration of reactive oxide ions and self-DC bias of substrate. At microwave power of 300, and 400 W, the high quality $SiO_2$ film that had lower surface roughness and defect in $Si/SiO_2$ interface was obtained. The value of interface trap density, then, was ${\sim}9{\times}10^{10}cm^{-2}eV^{-1}$.