• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.68-74
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• 2002

In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stark up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.11
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.18-27
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• 1996

By integrating WDM to OPS unit which plays an improtant role for the reliability of CPN, we made it possible to provide CATV, VOD, and high-speed data services simultaneously and to meet easily the requirements for new services in the future. For the design of optimal system, the link analysis of power budget has been perfomred. Also, the prototyped system has been tested with STM-1 level signals to confirm functions such as transmission, distribution, and protection. The results proved that when occurred out-of-order or recovery of ONU, the system did the pertinent switching with minimum loss for high-speed data services. Also for video distribution services, the system has distributed STM-1 level signals sucessfully.

• Journal of electromagnetic engineering and science
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• v.4 no.2
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• pp.56-62
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• 2004

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 ㎷) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-${\mu}{\textrm}{m}$ CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-㎓ RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.179-184
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• 2008

This paper presents the design of the feed forward controller to improve on the non-interference control performance of a single PWM converter in parallel for high-speed trains. The feed forward controller is designed to minimize the interference generated by converter switching in parallel operation of PWM converters. The gain value of the feed forward controller is calculated by inductance values of the input transformer. However, it is difficult to decide this gain value exactly because inductance values are changed by the operation condition of an input transformer. In this paper, the proposed design of feed forward controller can exactly decide the gain value using the leakage inductances estimated by detecting the variation of input current. the validity of the proposed feed forward controller is proved through the simulation results.

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.843-848
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• 2000

In general, inchworm actuators are composed of two clamping piezoelectric elements and one expansion piezoelectric element. In this paper, two electromagnetic clampers are used for higher speed and high load. Dynamic equation is derived to simulate the behavior of the inchworm actuator with electromagnets. Electromagnetic clamper is used to improve the performance of the inchworm actuator. The electromagnetic clamper is composed of two permanent magnets and one traditional electromagnet. The permanent magnets play the role of the source of magnetic field to make clamping force higher, and the electromagnet is to change the mode between clamping and free. The driving voltage profile is also analyzed to improve the speed of inchworm actuator. The real system was manufactured and experimented to find dynamic characteristics and the maximum speed is obtained. Dynamic model is verified by comparing with experimental results.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.684-686
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• 2000

Switched reluctance motor(SRM) has the advantages of simple structure, low rotor inertia. and high efficiency. However position sensor is essential in SRM in order to synchronize the phase excitation to the rotor position. The position sensors increase the cost of drive system and tend to reduce system reliability. This paper investigates the speed control of sensorless SRM in which the phase current and change rate are utilized in position decision, and the period of dwell angle is variable by compensating the rotor angle for speed control. The proposed system consists of position decision. phase locked loop controller, switching angle controller and inverter. The performances in the proposed system are verified through the experiment.

• Journal of KIEE
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• v.11 no.1
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• pp.62-68
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• 2001

In this paper it is proposed an advanced modified sliding mode control of a rotor field oriented control of induction motor. The application of this unconventional control has very good results, such as disturbance rejection and nice dynamic properties. Stability can be guaranteed even in the worst situation. A conventional "sliding mode" controller is characterised by fast switching control signal, which causes the chattering of the drive system. To overcome this problem, a modified law is used, by introducing a hysteresis band and a continuous control, which modifies the conventional law. The control is accomplished with dual TMS320C44 floating-point digital signal processor. The validity of the proposed method was verified by experiment on the propulsion system simulator, used for the development of Korean High-Speed Railway Train(KHSRT).in(KHSRT).

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.397-400
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• 2001

This paper presents a implementation of digital sensorless position control system of surface permanent-magnet synchronous motor (SPMSM) drive with a direct torque control (DTC). The system are stator flux and torque observer of stator flux feedback control model that inputs are current and voltage sensing of motor terminal with estimated rotor angle for a low speed operating area, two hysteresis band controllers, an optimal switching look-up table, rotor speed estimator, and IGBT voltage source inverter by using fully integrated control software. The developed sensorless control system are shown a good motion control response characteristic results and high performance features using 1.0 (kW) purposed servo drive SPMSM.

• Journal of Internet Computing and Services
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• v.3 no.3
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• pp.87-93
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• 2002

A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max＋plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.