• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 추계학술대회 논문집
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• pp.321-324
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• 2008

Recently, there is an increasing demand for efficient high power/weight auxiliary power supplies for use on high speed traction application. many new conversion techniques have been proposed to reduce the voltage and current stress of switching components, and the switching losses in the traditional pulse width modulation(PWM) converter. Among them, the phase shift full bridge zero voltage switching PWM techniques are thought most desirable for many applications because this topology permits all switching devices to operate under zero voltage switching(ZVS) by using circuit parasitic components such as leakage inductance of high frequency transformer and power device junction capacitance. The proposed topology is found to have higher efficiency than conventional soft-switching converter. Also it is easily applicable to phase shift full bridge converter by applying an energy recovery snubber consisted of fast recovery diodes and capacitors.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.233-233
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• 2000

Direct torque control (DTC) scheme provides a very quick torque response without the complex field-orientation block and inner current regulation loop. DTC is known as an appropriate scheme for high power induction motet drives because it can be used at lower switching frequency. There are two major drawbacks with the application of DTC schemes : one is large current harmonics due to flux drooping in a low speed range, the other is that the inverter switching frequency is varying according to motor parameters and operating speed. Switching devices in the power electronics drives should be supported for relatively high switching frequency. In this paper, a P-type fuzzy controller to realize the variable switching sector scheme and a PID-type fuzzy switching frequency regulator are adopted. A meaningful contribution of this paper is to propose a simple realization scheme of the fuzzy switching frequency regulator. Simulation results show the effectiveness of those propositions.

• ETRI Journal
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• 제38권1호
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.152.1-152
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• 2001

This paper presents a high performance and cost effective way by using an FPGA circuit to implement torque controller so that the SRM can operate at high speed. In order to increase the operating speed, we need to implement both the torque and the current controllers by using an FPGA. However, it is difficult to implement all of the torque controller in the FPGA. Moreover, implementation of a time critical part is sufficient for improving the performance. One of the time critical part is the switching angle control. In this study, torque controller which calculate the switching on and commutation angles is implemented in PC because these angle are a function of rotor velocity which is varied slowly, and switching angle controller ...

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.352-352
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• 2010

Silicon Carbide (SiC) power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this paper, we report the effect of the P-base doping concentration ($N_{PBASE}$) on the transient characteristics of 4H-SiC DMOSFETs. By reducing $N_{PBASE}$, switching time also decreases, primarily due to the lowered channel resistance. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimization of superior switching performance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.1133-1135
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• 1992

This paper describes high frequency inverter using zero voltage switching(ZVS). The ZVS operation is achieved to reduce the switching stress and switching loss under high speed switching. The proposed circuit configuration and performance are discussed. Its operation characteristics are evaluated through computer-aided simulation.

• 한국전자파학회논문지
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• 제14권8호
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• pp.809-815
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• 2003

OFDM/FH 시스템 등 고속 호핑을 요구하는 통신 시스템에서는 빠른 스위칭 속도와 낮은 위상잡음을 갖는 주파수 합성기가 필요하다. 본 논문에서는 기존의 PLL 주파수 합성기와 DH-PLL 주파수 합성기의 위상잡음과 스위칭 속도를 비교하고, OFDM/FH 시스템에 미치는 영향을 분석하였다. DH-PLL 주파수 합성기는 기존의 PLL 주파수 합성기에 비해 회로의 복잡도와 많은 전력 소모를 갖지만, 빠른 스위칭 속도를 갖고 있다. 일정한 루프필터 대역 하에서 위상잡음과 스위칭 속도가 반비례 관계를 갖고 있는 기존의 PLL 주파수 합성기와는 달리 DH-PLL 주파수 합성기는 매우 빠른 스위칭 속도와 낮은 위상잡음을 동시에 얻을 수 있다. 결과적으로 동일한 호핑 속도 요구를 만족해야 하는 경우 DH-PLL 주파수 합성기는 기존의 PLL 주파수 합성기보다 더 빠른 스위칭 속도와 더 적은 SNS손실을 얻을 수 있어 OFDM/FH 시스템 성능을 향상시킬 수 있다.

• Journal of Power Electronics
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• 제18권4호
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• 한국전자파학회논문지
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• 제16권2호
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• pp.167-173
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• 2005

직렬 PIN 다이오드 스위치의 격리도는 PIN 다이오드의 병렬 커패시턴스에 의해 제한을 받으며, 스위치 구동회로는 PIN 다이오드 스위치의 스위칭 속도를 제한한다. 이런 문제를 극복하기 위해, 병렬 공진 인턱턴스와 TTL 호환의 스위치 구동회로가 적용된 높은 격리도와 고속 스위칭의 PIN 다이오드 스위치를 제안하였다. 3 GHz PIN 다이오드 스위치의 측정 결과, 1 GHz의 주파수 대역폭, 1.5 dB 이내의 삽입 손실, 65 dB의 격리도, 15 dB 이상의 반사 손실 그리고 30 ns 이내의 스위칭 속도를 나타내었다. 특히, 병렬 공진 인덕턴스를 사용한 3 GHz스위치는 15 dB의 격리도 향상을 나타내었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 추계 기술심포지움 논문집
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• pp.33-36
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• 1999

In this paper, we proposed a simultaneous switching noise(SSN) reduction technique in muti-layer beards(MLB) for high-speed digital applications and analyzed them using the Finite Difference Time Domain(FDTD) method. The new method by conductive dielectric substrates reduces SSN couplings and resonances, significantly, which cause series malfunctions in the modem high-speed digital applications.