• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.67-70
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• 2000

DSP is used for processing the digital data in such as the multimedia applications. Because the digital data of high rate is demanded more and more, high performance is increasingly required in DSP. In this paper, we discuss important issues for development of high performance DSP, analyze architectures of several commercial DSP chips, and propose a new architecture. Finally, we show that the new architecture has the highest performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.5
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• pp.129-134
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• 2024

Radar signal processing boards have been widely used in embedded systems with architectures including DSPs and FPGAs. There is high-speed real-time communication between DSP and FPGA, high-speed real-time communication between DSP and DSP, and high-speed communication between FPGA and external radar components. This paper describes general communication interfaces such as memory and External Memory Interface (EMIF), HyperLink between DSP, SRIO (Serial Rapidio) between FPGA and DSP, PCIe (PCI Express), RS422 communication with FPGA and external components for DSP to boot, and describes how to implement high communication performance using these interfaces. In particular, high-speed communication between DSP and FPGA is explained by analyzing speed and performance. And previously, it describes how to receive a lot of information at high speed via RS422 communication, from the method of parallel processing individual signals through multiple signals in order to control the external radar components and receive information. The new method improves the communication speed and performance of the radar signal processing board.

• The Journal of the Korea Contents Association
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• v.8 no.5
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• pp.72-81
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• 2008

High Performance DSP usually supports cache and internal memory. For an optimal implementation of a multimedia stream application on such a high performance DSP, one needs to utilize the cache and internal memory efficiently. In this paper, we investigate performance analysis of cache, and internal memory configuration and placement necessary to achieve an optimal implementation of multimedia stream applications like motion picture encoder on high performance DSP, TMS320C6000 series, and propose strategies to improve performance for cache and internal memory placement. From the results of analysis and experiments, it is verified that 2-way L2 cache configuration with the remaining memory configured as internal memory shows relatively good performance. Also, it is shown that L1P cache hit rate is enhanced when frequently called routines and routines having caller-callee relationships with them are continuously placed in the internal memory and that L1D cache hit rate is enhanced by the simple change of the data size. The results in the paper are expected to contribute to the optimal implementation of multimedia stream applications on high performance DSPs.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.839-841
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• 2004

This paper presents a SPMSM servo motor drive system using high performance TMS320 F281T DSP for the industrial application. This high performance DSP contains some special peripheral circuits such as PWM (Pulse Width Modulation) waveform generation circuit, Quadrature Encoder Pulse (QEP) generation circuit and Analog to Digital Converter (ADC) circuit. In this paper, a servo drive control system is constructed using high performance DPS for the overall system cost reduction and the size minimization.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.258-261
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• 2003

This paper is a studying of the vector control of AC servo motor using a high performance DSP(TMX320F2812). This DSP has many special peripheral circuits to drive a AC Servo motor as AD converter, QEP and so on. It makes us reduce the time of developing a control system and also can be simple size controller. We use vector control algorithm for instantaneous torque control and SVPWM algorithm by offset voltage methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.72-81
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• 2002

A new high-performance DSP architecture is proposed, which behaves as a coprocessor of a 32bit microcontroller. Because the proposed DSP architecture is a dual MAC(Multiply and Accumulate) DSP architecture, it can process efficiently a number of SOP(sum of product) operations used in many DSP applications. In order to efficiently perform other operations such as pure additions without any restriction, a MAC is composed of a multiplier and a ALU placed in parallel. In addition, it is a 3-way superscalar architecture, which can issue 3 instructions at a time. The benchmark results with 3 thor dual MAC DSPs show that the proposed DSP has the best performance. Futhermore, it is proven that the proposed DSP is more efficient in memory usage, although the performance is comparable in some algorithms such as Viterbi decoding and FFT butterfly.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.3
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• pp.185-190
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• 2022

We propose a high speed data communication method for motor drive systems with fast control cycle in order to collect state variables of motor control without degrading control performance. Ethernet is chosen for communication device, and multi-core DSP architecture is exploited for communication processing load distribution. The communication program including network protocol stack and motor control program are assigned to two separate cores, and data between two cores are exchanged using interrupt-based inter-process communication mechanism, which enables to achieve a high-speed communication performance without degrading the motor control performance. The performance of developed communication method is demonstrated by real experiments using TCP, UDP and Raw Socket protocols in an experimental setup consisting of TI's TMS320F28388D motor control card and MS Windows PC.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.292-298
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• 1991

A new 6-axis robot controller with a high-speed 32-bit floating-point DSP TMS32OC30 has been developed in Samsung Electronics. The controller composed of Intel 80386 microprocessor for the main controller, and TKS32OC30 DSP chip for joint position controller. The characteristics of the controller are high sampling rate of 200us and fast reponsibility. The main controller supports MS-DOS, kinematics, trajectory planning, and sensor fusion functions which are vision, PLC, and MAP. The one high speed DSP chip is used for controlling 6 axes of a robot in 200us simultaneously. The control law applied is PID controller including a velocity feedforvard in joint position controller. The performance tests, such as command following, CP, were conducted for the controller integrated with a 6 axes robot developed in Samsung Electronics. The results showed a good performance. This controller can also perform the system control with other controllers, the communication with high priority controllers, and visual information processing.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.99-102
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• 2003

Computing environments of Embedded Systems are different from those of desktop computers so that they have resource constraints such as CPU processing, memory capacity, power, and etc.. Thus, when a desktop S/W is ported into embedded systems, optimization should be seriously considered. In this paper, we investigate several S/W optimization techniques to be considered for porting H.263 encoder into a high performance DSP, TMS320C6711. Through experiments, it is found that optimization techniques employed can make a big performance improvement.