• Title/Summary/Keyword: Heterostructure CMOS

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High Quality Ultrathin Gate Oxides Grown by Low-Temperature Radical Induced Oxidation for High Performance SiGe Heterostructure CMOS Applications (저온 래디컬 산화법에 의한 고품질 초박막 게이트 산화막의 성장과 이를 이용한 고성능 실리콘-게르마늄 이종구조 CMOS의 제작)

  • 송영주;김상훈;이내응;강진영;심규환
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.9
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    • pp.765-770
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    • 2003
  • We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

DC Characteristic of Silicon-on-Insulator n-MOSFET with SiGe/Si Heterostructure Channel (SiGe/Si 이종접합구조의 채널을 이용한 SOI n-MOSFET의 DC 특성)

  • Choi, A-Ram;Choi, Sang-Sik;Yang, Hyun-Duk;Kim, Sang-Hoon;Lee, Sang-Heung;Shim, Kyu-Hwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.99-100
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    • 2006
  • Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

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Development of SiGe Heterostructure Epitaxial Growth and Device Fabrication Technology using Reduced Pressure Chemical Vapor Deposition (저압화학증착을 이용한 실리콘-게르마늄 이종접합구조의 에피성장과 소자제작 기술 개발)

  • Shim, K.H;Kim, S.H;Song, Y.J;Lee, N.E;Lim, J.W;Kang, J.Y
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.4
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    • pp.285-296
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    • 2005
  • Reduced pressure chemical vapor deposition technology has been used to study SiGe heterostructure epitaxy and device issues, including SiGe relaxed buffers, proper control of Ge component and crystalline defects, two dimensional delta doping, and their influence on electrical properties of devices. From experiments, 2D profiles of B and P presented FWHM of 5 nm and 20 nm, respectively, and doses in 5×10/sup 11/ ∼ 3×10/sup 14/ ㎝/sup -2/ range. The results could be employed to fabricate SiGe/Si heterostructure field effect transistors with both Schottky contact and MOS structure for gate electrodes. I-V characteristics of 2D P-doped HFETs revealed normal behavior except the detrimental effect of crystalline defects created at SiGe/Si interfaces due to stress relaxation. On the contrary, sharp B-doping technology resulted in significant improvement in DC performance by 20-30 % in transconductance and short channel effect of SiGe HMOS. High peak concentration and mobility in 2D-doped SiGe heterostructures accompanied by remarkable improvements of electrical property illustrate feasible use for nano-sale FETs and integrated circuits for radio frequency wireless communication in particular.

Two Dimensional Boron Doping Properties in SiGe Semiconductor Epitaxial Layers Grown by Reduced Pressure Chemical Vapor Deposition (감압화학증착법으로 성장된 실리콘-게르마늄 반도체 에피층에서 붕소의 이차원 도핑 특성)

  • Shim, Kyu-Hwan
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.12
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    • pp.1301-1307
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    • 2004
  • Reduced pressure chemical vapor deposition(RPCYD) technology has been investigated for the growth of SiGe epitaxial films with two dimensional in-situ doped boron impurities. The two dimensional $\delta$-doped impurities can supply high mobility carriers into the channel of SiGe heterostructure MOSFETs(HMOS). Process parameters including substrate temperature, flow rate of dopant gas, and structure of epitaxial layers presented significant influence on the shape of two dimensional dopant distribution. Weak bonds of germanium hydrides could promote high incorporation efficiency of boron atoms on film surface. Meanwhile the negligible diffusion coefficient in SiGe prohibits the dispersion of boron atoms: that is, very sharp, well defined two-dimensional doping could be obtained within a few atomic layers. Peak concentration and full-width-at-half-maximum of boron profiles in SiGe could be achieved in the range of 10$^{18}$ -10$^{20}$ cm$^{-3}$ and below 5 nm, respectively. These experimental results suggest that the present method is particularly suitable for HMOS devices requiring a high-precision channel for superior performance in terms of operation speed and noise levels to the present conventional CMOS technology.