• Proceedings of the KIPE Conference
• /
• 2003.07b
• /
• pp.630-634
• /
• 2003

This paper proposes a Carrier-Rotation PWM technique that is new solution for the voltage unbalancing problem of flying capacitors in the Flying Capacitor Multi-level Inverter (FCMI).The proposed PWM technique equalizes the utilization of phase leg voltage redundancies corresponding to the charging and the discharging state of flying capacitors during one switching period of all the switches. it also has the same switch utilization and the reduced harmonics of output voltage. Hence, it is more suitable for the FCMI compared with the conventional solutions. Experimental results on the laboratory prototype flying capacitor 3-level inverter confirm the validity of the proposed PWM technique.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.1
• /
• pp.362-371
• /
• 2018

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.512-514
• /
• 2007

The number of transformers and the size of transformers in inverter using 3-phase transformer could be reduced compare with a multi-level inverter using single phase transformer. but still the 3-phase transformer inverter needs many switches. In this study, we proposed the isolated multi-level inverter using 3-phase transformers and common arm. Also, the equal-area method is used to calculate conduction angle with switching frequency equal to output fundamental frequency and it can reduce harmonics component of output voltage and switching loss. Finally, We tested multi-level inverter to clarify electric circuit and reasonableness through Matlab simulation and experiment by using prototype inverter.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1134-1135
• /
• 2007

In this paper, we proposed the isolated multi-level inverter using 3-phase transformers. It makes possible to use a single DC power source due to employing low frequency transformers. In this inverter, the number of transformer could be reduced comparing with an exiting 3-phase multi-level inverter using single phase transformer. Also, using phase angle control method with switching frequency equal to output fundamental frequency, harmonics component of output voltage and switching losses can be reduced. Finally, we made a prototype inverter to clarify the proposed electric circuit and reasonableness of control signal.

• Journal of Power Electronics
• /
• v.16 no.4
• /
• pp.1306-1315
• /
• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.1
• /
• pp.169-174
• /
• 2010

This paper explains end-point detection method for better speech recognition rates. The proposed method determines speech and non-speech region with the entropy and the harmonic detection of speech. The end-point detection using entropy on the speech spectral energy has good performance at the high SNR(SNR 15dB) environments. At the low SNR environment(SNR 0dB), however, the threshold level of speech and noise varies, so the precise end-point detection is difficult. Therefore, this paper introduces the end-point detection methods which uses speech spectral entropy and harmonics. Experiment shows better performance than the conventional entropy methods.

• Journal of Power Electronics
• /
• v.17 no.5
• /
• pp.1186-1194
• /
• 2017

This paper proposes an improved low frequency Selective Harmonic Mitigation-PWM (SHM-PWM) technique. The proposed method mitigates the low order harmonics of the output voltage up to the $50^{th}$ harmonic well and satisfies the grid codes EN 50160 and CIGRE-WG 36-05. Using a modified criterion for the switching angles, the range of the modulation index for non-linear SHM equations is improved, without increasing the switching frequency of the CHB converter. Due to the low switching frequency of the CHB converter, mitigating the harmonics of the converter up to the $50^{th}$ order and finding a wider modulation index range, the size and cost of the passive filters can be significantly reduced with the proposed technique. Therefore, the proposed technique is more efficient than the conventional SHM-PWM. To verify the effectiveness of the proposed method, a 7-level Cascaded H-bridge (CHB) converter is utilized for the study. Simulation and experimental results confirm the validity of the above claims.

• Proceedings of the KIPE Conference
• /
• 2008.06a
• /
• pp.85-87
• /
• 2008

The demand of a three phase PWM inverter for the purpose of power control or grid-connecting is increasing. This inverter is connected to a grid through an L-filter or LCL-filter to reduce the harmonics caused by switching. An LCL-filter can reduce the harmonic of a low switching frequency and generate a satisfactory level of grid side current with a relatively low-inductance than an L-filter. But the additional poles caused by the LC part affects a stability problem due to induced resonance of the system. This paper presents a compensation method using a power theory to improve performance, the designed LCL-filter system and to reduce the stability problems caused by resonance. The effectiveness of the proposed algorithm is verified by simulations.

• Journal of Power Electronics
• /
• v.17 no.3
• /
• pp.777-787
• /
• 2017

A new single phase half-bridge cascaded multilevel inverter based series active power filter (SAPF) is proposed. The main parts of the inverter are presented in detail. With the proposed inverter topology, any compensation voltage reference can be easily obtained. Therefore, the inverter acts as a harmonic source when the reference is a non-sinusoidal signal. A 31-level inverter based SAPF with the proposed topology, is manufactured and the voltage harmonics of the load connected to the point of common coupling (PCC) are compensated. There is no need for a parallel passive filter (PPF) since the main purpose of the paper is to represent the compensation capability of the SAPF without a PPF. It is aimed to compensate the voltage harmonics of the load fed by a non-sinusoidal supply using the proposed inverter. The validity of the proposed inverter based SAPF is verified by simulation as well as experimental study. The system efficiency is also measured in this study. Both simulation and experimental results show that the proposed multilevel inverter is suitable for SAPF applications.

• Journal of Power Electronics
• /
• v.16 no.6
• /
• pp.2162-2172
• /
• 2016

This paper presents a Direct Torque Control (DTC) strategy for the five-phase induction motor driven by a three-level five-phase inverter in order to improve the performance of the five-phase induction motor. In the proposed DTC technique, only 22 voltage vectors out of 243 available voltage vectors in a three-level five-phase inverter are selected and are divided in 10 sectors each with a width of $36^{\circ}$. The four different DTC combinations (DTC-I, II, III and IV) for a three-level five-phase induction motor drive are investigated for improving the performance of five-phase induction motor. All four of the DTC strategies utilize a combination of the same large and zero voltage vectors, but with different medium voltage vectors. Out of these four techniques, DTC-II gives the best performance when compared to the others. This DTC-II technique is analyzed in detail for improvements in the performance of five-phase induction motor in terms of torque ripple, x-y stator flux and Total Harmonics Distortion (THD) of the stator phase current when compared to its two-level counterparts. To verify the effectiveness of the proposed three-level five-phase DTC control strategy, a DSP based experimental system is build. Simulation and experimental results are provided in order to validate the proposed DTC technique.