• Proceedings of the KIEE Conference
• /
• 2005.07b
• /
• pp.1705-1707
• /
• 2005

This paper proposes a novel active frequency drift(AFD) method for the islanding prevention of grid-connected photovoltaic inverter. To detect the islanding phenomenon of grid-connected photovoltaic(PV) inverters concerning about the safety hazards and the damage to other electric equipments, many kinds of anti-islanding methods have been presented. Among them, AFD method using chopping fraction(cf) enables the islanding detection to drift up(or down) the frequency of the voltage during the islanding situation. However, the performance of the conventional AFD methods, which have a certain value of cf only, is inefficient and difficult to design the appropriate cf value analytically to meet the limit of harmonics. In this paper, the periodic chopping fraction based on an AFD method is proposed. This proposed method shows the analytical design value of cf to meet the test procedure of IEEE Std. 929-2000 with the power quality and islanding detection time. To verify the validation of the proposed method, the islanding test results are presented. It is confirmed that the proposed method has not only less harmonic distortion but also good performance of islanding detection compare with the conventional AFD method.

• Journal of Power Electronics
• /
• v.18 no.6
• /
• pp.1642-1649
• /
• 2018

A single-stage flyback LED AC-DC converter based on primary-side control under constant current mode is proposed in this study. The proposed converter features low total harmonic distortion (THD) and high power factor (PF). It also consists of a zero-crossing distortion compensation circuit and a variable duty ratio control compensation circuit to deal with the line current distortions caused by fixed duty ratio control. The system model and layout are built in Simplis and Cadence, respectively. The feasibility and performance of the proposed circuit is verified by designing and fabricating an IC controller in the HHNEC $0.35{\mu}m$ 5 V/40 V HVCMOS process. Experimental results show that the PF can reach a level in the range of 0.985-0.9965. Moreover, the average THD of the entire system is approximately 10%, with the minimum being 6.305%, as the input line voltage changes from 85 VAC to 265 VAC.

• Bulletin of the Korean Chemical Society
• /
• v.18 no.1
• /
• pp.56-61
• /
• 1997

Lead zirconate titanate (PZT) thin fills were deposited onto the Pt/Ti/SiO2/Si substrate by the pulsed laser deposition with the second harmonic wavelength (532 nm) of Nd:YAG laser. In order to determine the optimum conditions for the film deposition, the phase of the films were investigated as functions of ambient oxygen pressure, substrate temperature, and laser fluence. Also the chemical composition analysis was conducted for the PZT films deposited under various ambient oxygen pressure. When the distance between substrate and bulk PZT target is set to 20 mm, the optimum conditions have been determined to be 3 torr of oxygen pressure, 1.5 J/cm2 of laser fluence, and 823-848(±10) K range of substrate temperature. At these conditions, perovskite phase PZT films were obtained on platinized silicon. The chemical composition of the films is very similar to that of PZT bulk target. The physical structure of the deposited films analyzed by scanning electron microscopy shows a columnar morphology perpendicular to the substrate surface. Capacitance-Voltage hysteresis loop measurements show also a typical characteristics of ferroelectric thin film. The dielectric constant is found to be 528 for the 0.48 μm thickness of PZT thin film.

• Proceedings of the KSR Conference
• /
• 2009.05b
• /
• pp.499-503
• /
• 2009

In this study, the dynamic characteristic of a contact wire and pantograph suppling electrical power to high-speed trains are investigated from an electrical response point of view. To analysis power line disturbance by induced contact loss phenomenon for high speed operation, a hardware Simulator which considered contact loss between contact wire and the pantograph as well as contact wire deviation is developed. It is confirmed that a contact wire and pantograph model are necessary for studying the dynamic behavior of the pantograph system. One of the most important needs accompanied by increasing the speed of high-speed train is reduced that an arc phenomenon by loss of contact brings out EMI. In case of a high-speed train using electrical power, as comparison with diesel rolling stock, PLD(Power Line Disturbance) such as harmonic, transient voltage and current, EMI, dummy signal injection etc usually occurs. Throughout experiment, it is verified that an arc phenomenon is brought out for simulator operation and consequently conducted noise is flowed in electric circuit by power line disturbance.

• Computers and Concrete
• /
• v.20 no.6
• /
• pp.671-682
• /
• 2017

In this research, seismic response of pipes is examined by applying nanotechnology and piezoelectric materials. For this purpose, a pipe is considered which is reinforced by carbon nanotubes (CNTs) and covered with a piezoelectric layer. The structure is subjected to the dynamic loads caused by earthquake and the governing equations of the system are derived using mathematical model via cylindrical shell element and Mindlin theory. Navier-Stokes equation is employed to calculate the force due to the fluid in the pipe. Mori-Tanaka approach is used to estimate the equivalent material properties of the nanocomposite and to consider the effect of the CNTs agglomeration on the scismic response of the structure. Moreover, the dynamic displacement of the structure is extracted using harmonic differential quadrature method (HDQM) and Newmark method. The main goal of this research is the analysis of the seismic response using piezoelectric layer and nanotechnology. The results indicate that reinforcing the pipeline by CNTs leads to a reduction in the displacement of the structure during an earthquake. Also the negative voltage applied to the piezoelectric layer reduces the dynamic displacement.

• Journal of Power Electronics
• /
• v.19 no.2
• /
• pp.509-518
• /
• 2019

A novel islanding detection method is proposed in this paper. It is based on a frequency drooping PLL, which was presented in a previous work. The cause of errors in the non-detection zone (NDZ) of conventional frequency disturbance islanding detection methods (IDM) is analyzed. A frequency drooping phase-locked-loop (FD-PLL) is introduced into a single-phase grid-connected inverter (SPGCI), which can guarantee that grid current is in phase with the grid voltage. A novel FD-PLL IDM is proposed by improving this PLL. In order to verify the performance of the proposed FD-PLL IDM, a full performance comparison between the proposed IDM and typical existing active frequency drift IDMs is carried out, which includes both dynamic performance and steady performance. With the same NDZ, the total harmonic distortion of the grid-current in the dynamic process and steady state is analyzed. The proposed FD-PLL IDM, regardless of the dynamic or steady process, has the best power quality. Experimental and simulation results verify that the proposed FD-PLL IDM has excellent performance.

• Journal of Sensor Science and Technology
• /
• v.28 no.4
• /
• pp.240-245
• /
• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.26 no.3
• /
• pp.176-182
• /
• 2021

This research proposes a high-frequency circuit that can accurately predict the differential mode noise of single-phase inverters at the circuit design stage. Proposed single-phase inverter high frequency circuit in the work is a form in which harmonic impedance components are added to the basic single-phase inverter circuit configuration. For accurate noise prediction, parasitic components present in each part of the differential noise path were extracted. Impedance was extracted using a network analyzer and Q3D in the measurement range of 150 kHz to 30 MHz. A high-frequency circuit model was completed by applying the measured values. Simulations and experiments were conducted to confirm the validity of the high-frequency circuit. As a result, we were able to predict the resonance point of the differential mode voltage extracted as an experimental value with a high-frequency circuit model within an approximately 10% error. Through this outcome, we could verify that differential mode noise can be accurately predicted using the proposed model of the high-frequency circuit without a separate test bench for noise measurement.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.9
• /
• pp.71-80
• /
• 2007

This paper presents a new push-push VCO technique that extracts a second harmonic output signal from a capacitive commonnode in a negativegm oscillator topology. The generation of the $2^{nd}$ harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region that a conventional push-push technique using an emitter common node. Prototype 12GHz and 17GHz MMIC VCO were realized in GaInP/GaAs HBT technology. They have shown nominal output power of -4.3dBm and -5dBm, phase noise of -108 dBc/Hz and -110.4 dBc/Hz at 1MHz offset, respectively. The phase noise results are also equivalent to a VCO figure-of-merit of -175.8 dBc/Hz and -184.3 dBc/Hz, while dissipate 25.68mW(10.7mA/2.4V) and 13.14mW(4.38mA/3.0V), respectively.

• Journal of the Korean Society of Marine Environment & Safety
• /
• v.23 no.6
• /
• pp.739-745
• /
• 2017

Many studies have been conducted to reduce environmental pollution by ships and reduce fuel consumption. As part of this effort, research on power conversion systems through DC distribution systems that link renewable energy with conventional power grids has been pursued as well. The diode rectifiers currently used include many lower harmonics in the input current of the load and distort supply voltage to lower the power quality of the whole system. This distortion of voltage waveforms causes the malfunctions of generators, load devices and inverter pole switching elements, resulting in a large number of switching losses. In this paper, a controller is presented to improve DC output waveforms, the input Power Factor and the THD of an AFE type PWM rectifier used for PLL. DC output voltage waveforms have been improved, and the input Power Factor can now be matched to the unit power factor. In addition, the THD of the input power supply has been proven by simulation to comply with the requirements of IEEE Std514-2014.