• 전력전자학회논문지
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• 제7권4호
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• pp.359-365
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• 2002

최근 상업용 빌딩, 주거용 빌딩 및 공장등의 저전압 3상 4선식 배전계통에서 PC, UPS, 정류기기, 조명장치 및 사무용기기등 비선형 부하의 사용이 증가하고 있으며, 이로 인한 과도한 중성선 전류는 중성선의 고장, 변압기의 과열 및 중성선과 접지사이의 전압강하등 심각한 문제를 야기시키고 있다. 본 논문에서는 3상 4선식 배전계통에서 중성선 전류 제거를 위한 새로운 저감된 용량의 능동전력필터를 제안한다. 제안한 방식은 제어가 간단하고 불평형에 기인하는 기본파 전류만이 인버터 스위치로 흐를 수 있기 때문에 인버터의 VA 정격이 작아진다. 제안한 시스템은 실험에 의하여 그 타당성을 입증한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 춘계학술대회 논문집 전기설비전문위원
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• pp.48-50
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• 2006

SC(Static Condenser) in KEPCO is used in voltage control and power factor compensation. Currently KEPCO uses SC to 154kv 50MVA and 23kv SMVA. It is not important in old days because a SC bank accident has no effect on power system. But we are interested in the SC bank for power quality in these days. The SC Bank has a reactor and a condenser using series connection. It is operated in critical point for resonance circuit normally. Therefore the SC bank has a small reliability against other Power instruments. If a 4th harmonic frequency as a resonance frequency is supplied in system, the condenser is damaged because of a resonance current. And a trip and a closing for CB(Circuit Breaker) in many times will have a big influence of SC bank destruction. General OCR(Over Current Relay) observing SC bank is not useful for this protection We think that protection relay must be have the SC bank characteristics. A solution for this problem is active Power, resonance frequency and impedance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.499-504
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• 2017

A UHF CMOS variable gain low-noise amplifier (LNA) is designed for mobile digital TV tuners. The proposed LNA adopts a feedback topology to cover a wide frequency range from 474 to 868 MHz, and it supports the notch filter function for the interoperability with the GSM terminal. In order to handle harmonic distortion by strong interferers, the gain of the proposed LNA is step-controlled while keeping almost the same input impedance. The proposed LNA is implemented in a $0.11{\mu}m$ CMOS process and consumes 6 mA at a 1.5 V supply voltage. In the measurement, it shows the power gain of greater than 16 dB, NF of less than 1.7 dB, and IIP3 of greater than -1.7 dBm for the UHF band.

• 전력전자학회논문지
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• 제20권3호
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• pp.290-295
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• 2015

Analysis and verification of reactive power compensator (RPC) for ITER pulsed power electric network (PPEN) are described in this paper. The RPC system is rated for a nominal power of 250 Mvar necessary to comply with the allowable reactive power limit value from the grid 200 Mvar. This system is currently under construction and is based on static var compensation technology with a thyristor-controlled reactor and a harmonic filter. The RPC minimizes reactive power from grid using prediction of reactive power consumption of AC-DC converters. The feasibility of the reactive power compensation was verified by assembling a real controller and implementing ITER PPEN in the real time digital simulator for the hardware-in-loop facility. When maximum reactive power is reached, grid voltage is stabilized and maximum reactive power decreased from 120 Mvar to 40 Mvar via the reactive power prediction method.

• 전력전자학회논문지
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• 제17권6호
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• pp.478-485
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• 2012

In this paper, a new PWM method is proposed to reduce the input current harmonics of 3 phase PWM rectifier. In the conventional carrier comparison PWM method, a triangular wave is generally used as the carrier wave. However, the large d-axis current ripple by the triangle carrier wave may be a source of large input current THD(Total Harmonic Distortion). In this paper, a new carrier comparison PWM method with saw tooth wave is proposed. Depending on the sector where the voltage command vector places, one of the rising or falling saw tooth wave is selected. To reduce the switching losses of the saw tooth carrier PWM, the discontinuous PWM is also presented. The proposed PWM method can reduce the d-axis current ripple as well as the switching losses. The performance of the conventional and proposed PWM methods is verified by the simulation and experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.296-300
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• 1989

The paper proposes a method to eliminate harmonics of PWM inverter fed induction motor system using Walsh series. In other words, this paper presents technique of the selective harmonics elimination(SHE) by W-FT series in three phase PWM inverter output waveform. A microprocessor(8086 CPU) - controlled three phase induction motor system in order to verify this algorithm is present. It is designed for a three output voltage in the 1$\sim$60 Hz inverter with the 5th and 7th harmonics, 5th, 7th, 11th, and 13th, harmonics eliminated, and with the fundamental wave amplitude proportional to the output frequency. In the PWM inverter, dead time circuit is inserted in the switching si gnats to prevent the de link shortage. This paper is deals with quantative prediction of dead-time effect and its compensation in PWM inverters. The performance of the compensation circuits is confirmed by the experiment.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2668-2670
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• 1999

In the past, the PWM converter had a large switching loss by hard switching and difficult to high frequency operation. The resonance converter to decrease the switching loss and EMI is required the frequency control and needed to reduce the voltage or current stress at each parts. So, this paper propose the 3-phase boost converter and the method to compensated input power factor by control the amplitude - an instantaneous value of the DC inductor current -and control the switching frequency that a modulation error by the ripple of the DC inductor current. The proposed 3-phase PWM boost converter of single phase control type can takes higher capacity and compensate the power factor by using Feed back controller at each phase for the existing 3-phase bridge rectifier type. Moreover the 3-phase full bridge type using the rectifier at each 3-phase circuit will be small size reactor and compensate input power factor by minimize harmonic components of each phase.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.634-637
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• 1997

This paper is on the research and development of new SIV(Static Inverter) using IGBT(Insulated Gate Bipolar Transistor) semiconductor for a wide range of electric railway applications. For the simplification and higher controllability, the direct PWM control method with 3level inverter topology was adopted. In the new SIV system, the cost as well as bulk and weight was appreciably reduced about 40% lower than those of conventional SIV, the electrical efficiency was increased above 95% and the audible noise level was less than 65dB. In addition, the THD(Total Harmonic Distortion) factor was below 5% and the voltage fluctuation on a transient state was below 10%.

• Journal of Power Electronics
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• 제9권2호
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• pp.215-223
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• 2009

A design methodology for transformers including integrated and center-tapped structures for LLC resonant converters is proposed. In the LLC resonant converter, the resonant inductor in the primary side can be merged in the transformer as a leakage inductance. And, the absence of the secondary filter inductor creates low voltage stress on the secondary rectifiers and is cost-effective. A center-tapped structure of the transformer secondary side is widely used in commercial applications because of its higher efficiency and lower cost than full-bridge structures in the rectifying stages. However, this transformer structure has problems of resonance imbalance and transformer inefficiency caused by leakage inductance imbalance in the secondary side and the position of the air-gap in the transformer, respectively. In this paper, gain curves and soft-switching conditions are derived by first harmonic approximation (FHA) and operating circuit simulation. In addition, the effects of the transformer including integrated and center-tapped structures are analyzed by new FHA models and simulations to obtain an optimal design. Finally, the effects of the air-gap position are analyzed by an electromagnetic field simulator. The proposed analysis and design are verified by experimental results with a 385W LLC resonant converter.

• Journal of Power Electronics
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• 제7권1호
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• pp.64-71
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• 2007

This paper proposes a novel active frequency drift (AFD) method to improve the islanding detection performance with minimum current harmonics. To detect the islanding phenomenon of grid-connected photovoltaic (PV) inverters concerning the safety hazards and possible damage to other electric equipment, anti-islanding methods have been described. The AFD method that uses chopping fraction (cf) enables the islanding detection to drift up (or down) the frequency of the voltage during the islanding situation. However, the performance of the conventional AFD method is inefficient and causes difficulty in designing the appropriate cf value to meet the limit of harmonics. In this paper, the periodic chopping fraction based on a novel AFD method is proposed. This proposed method shows the analytical design value of cf to meet the test procedure of IEEE Std. 929-2000 with power quality and islanding detection time. To verify the validation of the proposed method, the islanding test results are presented. It is confirmed that the proposed method has not only less harmonic distortion but also better performance of islanding detection compared with the conventional AFD method.