• Journal of Electrical Engineering and Technology
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• 제7권1호
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• pp.1-8
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• 2012

The current paper presents a novel control strategy of a three-phase, four-wire Unified Power Quality (UPQC) to improve power quality. The UPQC is realized by the integration of series and shunt active power filters (APF) sharing a common dc bus capacitor. The realization of shunt APF is carried out using a three-phase, four-leg Voltage Source Inverter (VSI), and the series APF is realized using a three-phase, three-leg VSI. To extract the fundamental source voltages as reference signals for series APF, a zero-crossing detector and sample-and-hold circuits are used. For the control of shunt APF, a simple scheme based on the real component of fundamental load current (I $Cos{\Phi}$) with reduced numbers of current sensors is applied. The performance of the applied control algorithm is evaluated in terms of power-factor correction, source neutral current mitigation, load balancing, and mitigation of voltage and current harmonics in a three-phase, four-wire distribution system for different combinations of linear and non-linear loads. The reference signals and sensed signals are used in a hysteresis controller to generate switching signals for shunt and series APFs. In this proposed UPQC control scheme, the current/voltage control is applied to the fundamental supply currents/voltages instead of fast-changing APF currents/voltages, thus reducing the computational delay and the required sensors. MATLAB/Simulink-based simulations that support the functionality of the UPQC are obtained.

• Journal of international Conference on Electrical Machines and Systems
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• 제1권2호
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• pp.79-84
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• 2012

In this paper, a three-phase high-voltage converter (HVC), in which the main structure of each phase is composed of a cascaded PWM rectifier (CPR) and cascaded inverter (CI), is studied. A high-voltage grid is the input of the HVC. In order to ensure proper operation of the HVC, the control method should achieve output voltage sharing (OVS) among the rectifiers in the CPR, OVS among the inverters in the CI, and high power factor. Master-slave direct-current control (MDCC) is used to control the CPR. The ability of the control system to prevent interference is strong when using MDCC. The CI is controlled by three-loop control, which is composed of an outer common-output-voltage loop, inner current loops and voltage sharing loops. Simulation results show low total harmonic distortion (THD) in the HVC input currents and good OVS in both the CPR and CI.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.451-455
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• 1991

The PWM control technique is proposed which can eliminate the harmonic components of the nonsinusoidal ac line current such as the current of 6-phase rectifier by injecting PWM current. TSC(Time-Sharing Control) is adopted to avoid the unbalance between three PWM injection currents at the three-phase system. Also a new power circuit for three-phase filter is suggested for realizing the proposed PWM control technique. The operation characteristics are investigated theoretically and experimentally to show the feasibility of the optimized injection method.

• 전력전자학회논문지
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• 제4권5호
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• pp.423-432
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• 1999

This paper proposes a 12­pulse diode rectifier system with low kVA components suitable for powering switch mode power supplies or ac/dc converter applications. The proposed 12-pulse system employs a polyphase transformer, a zero sequence blocking transformer (ZSBT) in the dc link, and an interphase transformer. Results produce near equal leakage inductance in series with each diode rectifier bridge ensuring equal current sharing and performance improvements, The utility input currents and the voltage across the ZSBT are analyzed the kVA rating of each component in the proposed system is computed. The 5th , 7th , 17th and 19th harmonics are eliminated in the input line currents resulting in clean input power. The dc link voltage magnitude generated by the proposed rectifier system is nearly identical to a conventional to a conventional 6-pulse system. The proposed system is suitable to retrofit applications as well as in new PWM drive systems. Simulation and experimental results from a 208V , 10kVA system are shown.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 추계학술대회 논문집
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• pp.169-170
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• 2016

여러 분산 발전 시스템으로 구성된 마이크로그리드는 계통 연계 모드에서 부하의 수요에 담당하게 되고, 계통 사고가 발생할 시 독립 운전 모드로 동작을 해야 한다. 본 논문에서는 독립운전 모드 동작 시 제어 방식 중에서 유, 무효 전력제어를 통한 적절한 전력 분담을 실현하기 위한 드룹제어 방식을 다룬다. 이 방식은 선로 임피던스가 복합 성분으로 구성되어 있거나 불 평형 일 경우 여러 문제로 유,무효 전력 분담의 오차를 발생 시킨다. 이에 대하여 가상임피던스를 추가함으로써, 복합적 불 평형 임피던스에 기인한 유,무효 전력 분담의 오차를 해결 하여, 시스템의 유,무효 전력 분담을 개선 하고자 하였다. 또한, 비선형 부하 시 고조파의 문제를 비례-공진 제어기를 이용하여 고조파를 저감 할 수 있도록 하였다. 이에 PSIM 시뮬레이션과 실험을 통하여 검증하였다.

• Journal of Electrical Engineering and Technology
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• 제9권3호
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• pp.1104-1111
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• 2014

The digital substations are being built based on the IEC 61850 network. The cooperation and protection of power system are becoming more intelligent and reliable in the environment of digital substation. This paper proposes a novel method to prevent the malfunction caused by the Transformer Magnetizing Inrush Current(TMIC) using the IEC 61850 based data sharing between the IEDs. To protect a main transformer, the current differential protection(87T) and over-current protection(50/51) are used generally. The 87T IED applies to the second harmonic blocking method to prevent the malfunction caused by the TMIC. However, the 50/51 IED may malfunction caused by the TMIC. To solve that problem, the proposed method uses a GOOSE inter-lock signal between two IEDs. The 87T IED transmits a blocking GOOSE signal to the 50/51 IED, when the TMIC is detected. The proposed method can make a cooperation of digital substation protection system more intelligent. To verify the performance of proposed method, this paper performs the real time test using the RTDS (Real Time Digital Simulator) test-bed. Using the RTDS, the power system transients are simulated, and the TMIC is generated. The performance of proposed method is verified in real-time using that actual current signals. The reaction of simulated power system responding to the operation of IEDs can be also confirmed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.