• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• Journal of the Semiconductor & Display Technology
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• v.13 no.1
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• pp.73-81
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• 2014

In this paper, high-speed Hybrid MAC (Medium Access Control layer) implementation suitable for smart grid applications is researched. MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) is considered for high-speed communication method in smart grid application. In this paper, the MAC adopts the distributed network managing method. Also, the MB-OFDM merit of high-speed transfer rate of up to 480Mbps must be supported. Hence, this paper presents an efficient hardware-software integration (co-design) method in order to realize a high- speed transmission, and a realizing method of distribution network. Finally, MAC performance and reliability based on MB-OFDM PHY (PHYsical layer) are confirmed through simulation and emulation.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.2
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• pp.8-17
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• 2008

This paper presents the Matlab/Simulink-based software-in-the-loop simulation(SILS) environment which is the co-simulator for temporal and functional simulations of control systems. The temporal behavior of a control system is strongly dependent on the implemented software and hardware such as the real-time operating system, the target CPU, and the communication protocol. The proposed SILS abstracts the system with tasks, task executions, real-time schedulers, and real-time networks close to the implementation. Methods to realize these components in graphical block representations are investigated with Matlab/Simulink, which is most commonly used tool for designing and simulating control algorithms in control engineering. In order to achieve a seamless development from SILS to rapid control prototyping (RCP), the SILS block-set is designed to support automatic code generation without tool changes and block modifications.

• Journal of Internet Computing and Services
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• v.25 no.1
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• pp.29-37
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• 2024

In this paper, we propose an efficient image processing system to detect and track the movement of specific objects such as patients. The proposed system extracts the outline area of an object from a binarized difference image by applying a thinning algorithm that enables more precise detection compared to previous algorithms and is advantageous for mixed-mode design. The binarization and thinning steps, which require a lot of computation, are designed based on RTL (Register Transfer Level) and replaced with optimized hardware blocks through logic circuit synthesis. The designed binarization and thinning block was synthesized into a logic circuit using the standard 180n CMOS library and its operation was verified through simulation. To compare software-based performance, performance analysis of binary and thinning operations was also performed by applying sample images with 640 × 360 resolution in a 32-bit FPGA embedded system environment. As a result of verification, it was confirmed that the mixed-mode design can improve the processing speed by 93.8% in the binary and thinning stages compared to the previous software-only processing speed. The proposed mixed-mode system for object recognition is expected to be able to efficiently monitor patient movements even in an edge computing environment where artificial intelligence networks are not applied.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.687-688
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• 2011

This paper presents a design method for combinational digital logic systems using time domain based multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.3
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• pp.261-266
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• 2004

Recently, a variety of intelligent robots are developed for the personal purpose beyond the industrial application. These intelligent robots have ranges of sensors, actuators, and control algorithms to their application. In this paper we propose a reconfigurable robot controller, $SR^2$c (The SOPC-based Reconfigurable Robot Controller), based on SOPC (System on a Programmable Chip), that can be reconfigurable easily by software. The proposed robot controller contains not only a processing module but also robot-specific IP's. To show a feasibility of the proposed robot controller, a small entertainment robot, Wizard-4 is implemented with a single chip controller as proposed in this paper.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.126.4-126
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• 2001

Recently, researches on CIM in product lines of industrial plant are widely progressed, automation of working environment with modernization of product equipments is realized and also, installation of integrated control system based on computer is activated. Since the CIM system is basically developed by using computer, there are several complicated problems such as design problem of hardware interface between computer and many product machines with individual special functions, software development problem with realtime data process and multi communication functions for realtime data monitoring and control of product machines This paper shows the development results for a single board type of microcontroller and a monitoring software based on realtime processing database system ...

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.520-523
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• 2008

As a result of the recent development of the electro-information industry, the hardware of an automated ultrasonic testing system is getting lighter and diversified image processing techniques are applied to its software so that the possible precise totaling and detecting of the flaws are studied. This study proposes an automated ultrasonic testing system of the pipe in order to organize the optimized system, and also describes the data flow and general composition of the software for the design of the system.