• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.

• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Journal of Advanced Navigation Technology
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• v.17 no.1
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• pp.69-79
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• 2013

In this paper, DCT(Discrete Cosine Transform) and CAVLC(Context Adaptive Variable Length Coding) are co-designed as hardware IP with software operation of the other modules in H.264/AVC codec. In order to increase the operation speed, a new method using SHIFT table is proposed. As a result, enhancement of about 16(%) in the operation speed is obtained. Designed Hardware IPs are downloaded into Virtex-4 FX60 FPGA in the ML-410 development board and H.264/AVC encoding is performed with Microblaze CPU implemented in FPGA. Software modules are developed from JM13.2 to make C code. In order to verify the designed Hardware IPs, Modelsim program is used for functional simulation. As a result that all Hardware IPs and software modules are downloaded into the FPGA, improvement of processing speed about multiples of 16 in case of DCT hardware IP and multiples of 10 in case of CAVLC compared with software-only processing. Although this paper deals with co-design of H/W and S/W for H.264, it can be utilized for the other embedded system design.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1750-1756
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• 2011

After Kyoto Protocol was adopted for green gas reduction, each nations are stepping up efforts to reduce $CO_2$ of a typical green gas. Construction industry also is trying $CO_2$ reduction with the techniques of two types which are software and hardware techniques. The software technique are Passive Design considered green gas emission and the environment impact assessment by LCA. The hardware techniques are adjustment of equipment system and development of eco- friendly material. But, it is nonexistent that a study related to $CO_2$ emission considered detail process in construction industry. This study analyzed the relativeness of equipment combination and $CO_2$ emission by calculate $CO_2$ emission follow to equipment combination on earth-work which is the process emitted most $CO_2$ among railway bedding construction.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.204-207
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• 2000

Verification is one of the most critical and time-consuming tasks in today's design process. This paper describes the basic idea of Co-verification and the environment setup for the design of DVD Servo with TeakLite DSP core by using Seamless CVE, Hardware/software Co-verification too1.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.237-239
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• 2001

This paper describes the digital relay simulator system using digital signal processor. The simulator system has two parts, one is software and the other is hardware part. The simulation software has variety calculation engines ; EMTP simulation data file conversion, user define simulation data generation, sequence data generation, data analysis engines. etc, these are designed upon GUI. And simulator software provides easy control interface for users, the simulator software performs on every MS Windows OS. The simulator hardware design uses 32bit floating point DSP(TMS320C32) architecture to achieve flexibility and high speed operation.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.140.4-140
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• 2001

This paper presents the duplex controller operated as master slave for Self Excited Static Type excitation system and the results of operation for duplex digital excitation system. Software is made up duplex multi-tasking control algorithm which is based on VxWorks(real-time OS), preprocessing algorithm for input-output signal, BSP & Device Driver for interfacing hardware and software, and OIS(Operator Interface Station) program, HMI S/W. Master controller and slave controller intercommunicate dominant data to minimize bump when controller switchover from master to slave occurs. Communication between master controller and slave controller is duplicated and communication between OIS and controller is duplicated. Hardware is made up VMEBUS based controller which is designed with PPC & I/O board ...