• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.504-505
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• 2014

In this paper, by using hardware in the loop(HIL) of the EES, which is an inverter of high-rated technique and analyze the function. By exchanging information between the simulation and system controller to be used in a live system, HIL approach, approach experimental is used to interpret the system mass analysis is not possible in a real system some. This paper presents the implementation of the EES and the RTDS DSP28335 is a real-time connection to the electrical signal, and to verify the actual system is difficult, it was possible to analyze the performance of the system. Thus, it is expected to contribute I raise the stability and reliability of the operation during the actual EES is built.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1707-1721
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• 2004

In this paper, we propose a distributed communication model of intrusion detection system(IDS) in which integrated security management at networks level is possible, model it at a security node and distributed system levels, design and implement a simulator. At the node level, we evaluate the transfer capability of alert message based on the analysis of giga-bit security node architecture which performs hardware-based intrusion detection. At the distributed system level, we perform the evaluation of transfer capability of detection and alert informations between components of distributed IDS. In the proposed model, we carry out the performance evaluation considering decision factors of communication mechanism and present the results in order to gain some quantitative understanding of the system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.555-562
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• 2007

In order to display Bayer input stream received from CMOS image sensor to the display device, image signal processing must be performed. That is, the hardware performing the image signal processing for Bayer data is called ISP(Image Signal Processor). We can see real image through ISP processing. ISP executes functionalities for gamma correction, interpolation, color space conversion, image effect, image scale, AWB, AE and AF. In this paper, we obtained the optimum algorithm through software verification of ISP module for CMOS camera image sensor and described using VHDL and verified in ModelSim6.0a simulator. Also we downloaded into Xilinx XCV-1000e for the designed ISP module and completed the board level verification using PCI interface.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.75-81
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• 2021

This study analyzes the resonance characteristics caused by the mutual interference between LCL filters and the grid impedance under the parallel operation of the grid-connected inverter using the LCL filter. These characteristics are verified through simulation and experiment. Two inverters are used to connect to the grid in parallel, and the system parameters, including the LCL filter, are set to the same conditions. In the case of inverters running in parallel at the point of common coupling, the presence of grid impedance causes mutual interference between the LCL filters of each inverter, and the deviation of the filter resonance frequency is analyzed to understand the parallel inverter. The correlation between the number of devices and the size of grid impedance is simulated by PSIM and verified by MATLAB. By connecting the real-time digital simulator Typhoon HILS to the DSP 28377 control board, the mutual interference characteristics are tested under the condition of two inverters running in parallel. The experimental and analysis results are the same, indicating the validity of the analysis.

• Journal of Drive and Control
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• v.16 no.3
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• pp.67-74
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• 2019

The automotive market has recently been investing much time and costs in improving existing technologies such as ABS (Anti-lock Braking System) and TCS (Traction Control System) and developing new technologies. Additionally, various methods have been applied and developed to reduce this. Among them, the development method using the simulation has been mainly used and developed. In this paper, we have studied a method to develop SILS (Software In the Loop Simulation) for TCS which can test various environment variables under the same conditions. We modeled hardware (vehicle engine and ABS module) and software (control logic) of TCS using MATLAB/Simulink and Carsim. Simulation was performed on the climate, road surface, driving course, etc. to verify the TCS logic. By using SILS to develop TCS control logic and controller, it is possible to verify before production and reduce the development period, manpower and investment costs.

• Progress in Superconductivity and Cryogenics
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• v.25 no.4
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• pp.54-59
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• 2023

In this paper, we analyze experimental results by applying the PHILS model to a lab-scale superconducting current limiter system for its actual application in medium-voltage direct current (MVDC) systems. Superconducting current limiters exhibit effective current-limiting performance in circuit breaker operations, particularly in limiting large fault currents within a short period, addressing the challenges posed by the increasing use of renewable energy and the integration of DC medium-voltage distribution systems. The development of such superconducting current limiters faces various technical and cost disadvantages, especially when applying a medium-voltage 35kV level system, which is intended for future introduction. The proven lab-scale superconducting current limiter system and the PHILS model are combined and integrated into the actual system. Our plan involves analyzing the limiter's performance, assessing its impact on the system, and preparing for its application in future medium-voltage systems. Utilizing RTDS, a simulation was conducted by connecting actual scaled-down equipment and systems, with the analysis results presented.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• ETRI Journal
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• v.42 no.4
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• pp.491-504
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• 2020

We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on-chip memory. Complementing the hardware is an intuitive and user-friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40-TFLOP STC that includes 32k arithmetic units and over 36 MB of on-chip SRAM, our baseline implementation of AB9 consists of a 1-GHz quad-core setup with other various industry-standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general-purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28-nm process with a chip size of 17 × 23 ㎟. Delivery is expected later this year.