• Journal of the Korea Society for Simulation
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• v.29 no.1
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• pp.39-46
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• 2020

The utilization of artificial intelligence (AI) in the engagement has been a key research topic in the defense field during the last decade. To pursue this utilization, it is imperative to acquire a realistic simulation to train an AI engagement agent with a synthetic, but realistic field. This paper is a case study of training an AI agent to operate with a hardware realism in the air-warfare dog-fighting. Particularly, this paper models the pursuit of an opponent in the dog-fighting setting with a gun-only engagement. In this context, the AI agent requires to make a decision on the pursuit style and intensity. We developed a realistic hardware simulator and trained the agent with a reinforcement learning. Our training shows a success resulting in a lead pursuit with a decreased engagement time and a high reward.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.133-142
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• 2004

Recently, the growth of Internet and a variety of multimedia services through Internet increasingly demands high-speed packet transmission, the new routing function, and QoS guarantee on conventional routers. Thus, a new switching mechanical called the MPLS(Multi-Protocol Label Switching), was proposed by IETF(Internet Engineering Task Force) as a solution to meet these demands. In addition the deployment of MPLS network supporting Differentiated Services is required. In this paper, we propose the architecture of the MPLS switch supporting Differentiated Services in the MPLS-based network. The traffic conditioner consists of a classifier, a meter, and a marker. The VOQ-PHB module, which combines input Queue with each PHB queue, is implemented to utilize the resources efficiently. It employs the Priority-iSLIP scheduling algorithm to support high-speed switching. We have designed and verified the new and fast hardware architecture of VOQ-PHB and the traffic conditioner for QoS and high-speed switching using NS-2 simulator. In addition, the proposed architecture is modeled in VHDL, synthesized and verified by the VSS analyzer from SYNOPSYS. Finally, to justify the validity of the hardware architecture, the proposed architecture is placed and routed using Apollo tool.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.9
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• pp.1212-1218
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• 2014

For OBC (On-Board Charger) and LDC (Low DC-DC Converter) used as essential power conversion systems of PHEV (Plug-in Hybrid Electric Vehicle), system performance is required as well as reliability, which is need to protect the vehicle and driver from various faults. While current development processor is sufficient for embodying functions and verifying performance in normal state during development of prototypes for OBC and LDC, there is no clear method of verification for various fault situations that occur in abnormal state and for securing stability of vehicle base, unless verification is performed by mounting on an actual vehicle. In this paper, a CCM (Charger Converter Module) was developed as an integrated structure of OBC and LDC. In addition, diverse fault situations that can occur in vehicles are simulated by a simulator to artificially inject into power conversion system and to test whether it operates properly. Also, HILS (Hardware-in-the-Loop Simulation) is carried out to verify whether LDC is operated properly under power environment of an actual vehicle.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.2
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• pp.203-209
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• 2015

Recently, the portion of electronic control in an engine system has been increasing with the aim of meeting the requirements of emissions and fuel efficiency of the engine system in the construction machinery industry. Correspondingly, the complexity of the engine management system (EMS) has increased. This study developed an engine HiLS system for reducing the cost and time required for function development for the EMS. The engine model for HiLS is composed of air, fuel, torque, and dynamometer models. Further, the mean value method is applied to the developed HiLS engine model. This model is validated by its application to a heavy-duty diesel engine equipped with an exhaust gas recirculation system and a turbocharger. Test results demonstrate that the model has accuracy greater than 90 and also verify the feasibility of the virtual calibration process.

• Journal of Energy Engineering
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• v.7 no.1
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• pp.96-102
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• 1998

The use of computers as part of nuclear safety systems elicits additional requirements-software verification and validation (v/v), hardware qualification-not specifically addressed in general industry fields. The computer used in nuclear power plants is a system that includes computer hardware, software, firmware, and interfaces. To develop the computer systems graded with nuclear safety class, the developing environments have to be required in advance and the developed software have to be verified and validated in accordance with nuclear code and standards. With this requirements, the test facility for Inadequate Core Cooling Monitoring System (ICCMS) as one of safety systems in the nuclear power plants was developed. The test facility consists of three(3) parts such as Input/Output (I/O) simulator, Plant Data Acqusition System (PDAS) cabinets and supervisory computer. The performance of the system was validated by manual test procedure.

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1858-1865
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• 2007

In this paper, we introduce the design and implementation of satellite IP modem. The designed satellite IP modem shows the performance of 0.2% overhead, BER=10-5 when Eb/No=6dB, frequency offset of 8KHz, data rate up to 1536Kbps, $F_{if}=140MHz$. The designed system is verified through software simulation and then implemented with MPC86x communication processor, TMS320C6416 DSP, and Altera FPGA. Since each hardware unit is implemented in daughter board for modularity, we can reduce the development time and easily improve the performance with using better processor. Linux is used for embedded OS because it shows better performance in IP manipulation multitask processing, and hardware control through device driver. The implemented system is tested and verified with channel simulator. Since the proposed IP modem shows small size and light weight, that can be used anywhere with easy if you need IP environment.

• Journal of the Korea Society of Computer and Information
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• v.25 no.4
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• pp.1-9
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• 2020

In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.153-164
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• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.