• Journal of KIISE:Computing Practices and Letters
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• v.15 no.8
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• pp.547-565
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• 2009

Simulation is the imitation of some real thing, state of affairs, or process. The act of simulating something generally entails identifying certain key characteristics or behaviors of a selected physical or abstract system. And a simulator is the software or hardware tool that performs simulation tasks. When developing a simulator, the non-functional requirements such as modifiability, interoperability, and extendability should be required. However, existing studies about the simulator development focus not on such non-functional requirements but on the methodologies to build the simulation model. In this paper, we suggest the new architectural pattern for the software based simulator in consideration of such non-functional requirements. In order to define the architectural pattern, we identify the essential elements of the simulators, define relationships between them, and design the architectural structure with the elements to accommodate such non-functional requirements. According to the proposed pattern we can solve the simulation problems to combine the various simulation model components. The pattern guarantees modifiability by reconstructing the simulation model, also guarantees interoperability and extendability by adding various interfaces to the simulation model and by keeping the consistent interfacing mechanism between the simulation model components. The suggested architectural pattern can be used as the reference architecture of the simulator systems that will be developed in future.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.1
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• pp.42-56
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• 2002

It is possible but not efficient to model and simulate asynchronous microprocessors with the existing HDLs(HARDware Description Languages) such as VHDL or Verilog. The reason it that the description becomes too complex. and also the simulation time becomes too long to explore the design space. Therefore it is necessary to establish a methodology and develop a tool for modeling the handshake protocol of asynchronous microprocessors very easily and simulating it very fast. Under this objective an efficient CAD(Computer Aided Design) tool SLEDS(System Level Event-Driven Simulator) was developed which can evaluate performance of a processor through modeling with a simple description an simulating with event driven engine in the system level. The ultimate goal in the tool SLEDS is to fin the optimal conditions for a system to produce high performance by balancing the delay of each module in the system. Besides SLEDS aims at verifying the design through comparing the expected results with the actual ones by performing the defined behavior.

• Journal of Satellite, Information and Communications
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• v.6 no.1
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• pp.68-74
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• 2011

In this paper, we present the enhancement results such as availability and accuracy using the GPS L1 and Galileo E1 signal combination. To enhance the acquisition and tracking performance of signal processing in GNSS receiver. several tracking loops with integrator, discriminator, and loop filter module are applied. Also, this paper presents the performance comparison results between prototype receiver equipped with hardware board and software receiver. Also the tracking loop performance of real hardware receiver is verified by comparing with tracking accuracy, sensitivity occurred by the Spirent simulator. Especially, to process the Galileo E1 signal, it is used the a power early late type which is the typical type for DLL discriminator.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2011.11a
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• pp.544-547
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• 2011

This paper describes on hardware simulation of passive power control of propulsion system for electric propulsion aircraft of KARI. The propulsion system uses hybrid power system that is composed of solar cell, fuel cell and battery. The fuel cell is replaces by simulator due to its difficulty in handling while the other components are the same as that will be used on board. As the result, reliable power supply for propulsion is confirmed and each power source is well operated showing its characteristics.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.22-32
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• 1997

This paper proposes an imprecise compuitation model for DCT considering QOS of images and a two dimensional DCT architecture for imprecise computations. In case that many processes are scheduling in a hard real time system, the system resources are shared among them. Thus all processes can not be allocated enough system resources (such as processing power and communication bandwidth). The imprecise computtion model can be used to provide scheduling flexibility and various QOS(quality of service)levels, to enhance fault tolerance, and to ensure service continuity in rela time systems. The DCT(discrete cosine transform) is known as one of popular image data compression techniques and adopted in JPEG and MPEG algorithms since the DCT can remove the spatial redundancy of 2-D image data efficiently. Even though many commercial data compression VLSI chips include the DCST hardware, the DCT computation is still a very time-consuming process and a lot of hardware resources are required for the DCT implementation. In this paper the DCT procedure is re-analyzed to fit to imprecise computation model. The test image is simulated on teh base of this model, and the computation time and the quality of restored image are studied. The row-column algorithm is used ot fit the proposed imprecise computation DCT which supports pipeline operatiions by pixel unit, various QOS levels and low speed stroage devices. The architecture has reduced I/O bandwidth which could make its implementation feasible in VLSI. The architecture is proved using a VHDL simulator in architecture level.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.416-419
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• 2003

The cellular neural networks have the circuit structure that differs from the form of general neural network. It consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template property. In this paper, time-multiplex image processing technique is applied for processing large images using small size CNN cell block, and we simulate the edge detection of a large image using the simulator implemented with a c program and matlab model. A 5$\times$5 CNN hardware and pre post processor is also implemented and is under test.

• Journal of Ocean Engineering and Technology
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• v.30 no.5
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• pp.367-373
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• 2016

This paper describes the development of a navigation HILS (hardware in the loop simulation) system for an integrated navigation performance analysis of a large diameter unmanned underwater vehicle (LDUUV). The HILS system was used for the performance analysis of the LDUUV. When a conventional HILS system is used, it is not possible to calculate the velocity and position using an inertial navigation system (INS). To cope with this problem, an external acceleration was generated. To evaluate the proposed method, we compare the results of a Monte Carlo simulation and navigation HILS experiment.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.41-48
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• 2018

This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.150-157
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• 2021

Nowadays, a DC microgrid that can link various distributed power sources is gaining much attention. Accordingly, research on fault situations, such as line-to-line and line-to-ground faults of the DC microgrid, has been conducted to improve grid reliability. However, the blackout of an AC system and the oscillation of a DC bus voltage have not been reported or have not been sufficiently verified by previous research. In this study, a 20 kW DC microgrid testbed using a power HIL simulation technique is proposed. This testbed can simulate various fault conditions without any additional grid facilities and dangerous experiments. It includes the blackout of the DC microgrid caused by the AC utility grid's blackout, a drastic load increment, and the DC bus voltage oscillation caused by the LCL filter of the voltage source converter. The effectiveness of the proposed testbed is verified by using Opal-RT's OP5707 real-time simulator with a 3 kW prototype three-port dual-active-bridge converter.

• The Journal of Korea Robotics Society
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• v.17 no.3
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• pp.373-380
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• 2022

This paper considers a method of fast correspondence matching for iterative closest point (ICP) algorithm. In robotics, the ICP algorithm and its variants have been widely used for pose estimation by finding the translation and rotation that best align two point clouds. In computational perspectives, the main difficulty is to find the correspondence point on the reference point cloud to each observed point. Jump-table-based correspondence matching is one of the methods for reducing computation time. This paper proposes a method that corrects errors in an existing jump-table-based correspondence matching algorithm. The criterion activating the use of jump-table is modified so that the correspondence matching can be applied to the situations, such as point-cloud registration problems with highly curved surfaces, for which the existing correspondence-matching method is non-applicable. For demonstration, both hardware and simulation experiments are performed. In a hardware experiment using Hokuyo-10LX LiDAR sensor, our new algorithm shows 100% correspondence matching accuracy and 88% decrease in computation time. Using the F1TENTH simulator, the proposed algorithm is tested for an autonomous driving scenario with 2D range-bearing point cloud data and also shows 100% correspondence matching accuracy.