• 제목/요약/키워드: Hardware redundancy

검색결과 95건 처리시간 0.031초

An Unequal Protection FEC Scheme for Video over Optical Access Networks

  • Cao, Yingying;Chen, Xue;Wang, Liqian;Li, Xicong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제7권6호
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    • pp.1463-1479
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    • 2013
  • In this paper, we propose an unequal protection physical coding sub-layer (PCS) forward error correction (FEC) scheme for efficient and high-quality transmission of video data over optical access networks. Through identifying and resolving the unequal importance of different video frames and passing this importance information from MAC-layer to PCS, FEC scheme of PCS can be adaptive to application-layer data. Meanwhile, we jointly consider the different channel situations of optical network unit (ONU) and improve the efficiency of FEC redundancy by channel adaptation. We develop a theoretical algorithm and a hardware method to achieve efficient FEC assignment for the proposed unequal protection scheme. The theoretical FEC assignment algorithm is to obtain the optimal FEC redundancy allocation vector that results in the optimum performance index, namely frame error rate, based on the identified differential importance and channel situations. The hardware method aims at providing a realistic technical path with negligible hardware cost increment compared with the traditional FEC scheme. From the simulation results, the proposed Channel and Application-layer data Adaptation Unequal Protection (CAAUP) FEC scheme along with the FEC ratio assignment algorithm and the hardware method illustrates the ability of efficient and high-quality transmission of video data against the random errors in the channel of optical access networks.

틸트로터 무인기 비행제어컴퓨터 이중화 시스템 개발 (Development of FCC Redundancy System for Tiltrotor UAV)

  • 박범진;강영신;유창선;조암
    • 한국항공우주학회지
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    • 제45권2호
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    • pp.133-139
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    • 2017
  • 틸트로터 무인기의 비행제어컴퓨터는 신뢰도 향상을 위하여 주 채널과 보조 채널을 갖는 이중화 시스템으로 설계되었다. 이중화 기능은 채널 전환과 데이터 복원으로 구성된다. 채널 전환 기능은 교차채널 데이터링크를 이용한 소프트웨어 방식과 워치독 타이머를 이용한 하드웨어 방식으로 구성되었다. 데이터 복원 기능은 운용 중 비행제어컴퓨터가 비정상적으로 재시작 되었을 때 비행 상태를 유지하기 위한 기능이다. 이중화 기능은 비행제어컴퓨터 벤치 시험, 체계 통합 시험 그리고 HILS 시험을 통해 검증되었다. 본 논문에서는 틸트로터 무인기 비행제어컴퓨터에 구현된 이중화 기능과 시험-검증 방법에 대해서 기술하였다.

Fault Tolerance Design for Servo Manipulator System Operating in a Hot Cell

  • Jin, Jae-Hyun;Ahn, Sung-Ho;Park, Byung-Suk;Yoon, Ji-Sup;Jung, Jae-Hoo
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2003년도 ICCAS
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    • pp.2467-2470
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    • 2003
  • In this paper, fault tolerant mechanisms are presented for a servo manipulator system designed to operate in a hot cell. A hot cell is a sealed and shielded room to handle radioactive materials, and it is dangerous for people to work in the hot cell. So, remote operations are necessary to handle radioactive materials in the hot cell. KAERI has developed a servo manipulator system to perform such remote operations. However, since electric components such as servo motors are weak to radiations, fault tolerant mechanisms have to be considered. For fault tolerance of the servo manipulator system, hardware and software redundancy have been considered. In case of hardware, radioactive resistant electric components such as cables and connectors have been adopted and motors driving a transport have been duplicated. In case of software, a reconfiguration algorithm accommodating one motor's failure has been developed. The algorithm uses redundant axis to recover the end effector's motion in spite of one motor's failure.

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핫셀용 서보 매니퓰레이터 시스템의 내고장 설계 (Fault tolerant design of a Servo Manipulator System for Hot Cell Operation)

  • 진재현;박병석;안성호;윤지섭;정재후
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2003년도 추계학술대회
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    • pp.1464-1469
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    • 2003
  • In this paper, fault tolerant mechanisms are presented for a servo manipulator system designed to operate in a hot cell. A hot cell is a sealed and shielded room to handle radioactive materials, and it is dangerous for people to work in the hot cell. So, remote operations are necessary to handle the radioactive materials in the hot cell. KAERI has developed a servo manipulator system to perform such remote operations. However, since electric components such as servo motors are weakened with radiation, fault tolerant mechanisms have to be considered. For fault tolerance of the servo manipulator system, hardware and software redundancy has been considered. In the case of hardware, radioactive resistant electric components such as cables and connectors have been adopted and motors driving a transport have been duplicated. In case of software, a reconfiguration algorithm accommodating one motor's failure has been developed. The algorithm uses redundant axes to recover the end effector's motion in spite of one motor's failure.

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인공신경망을 이용하여 하드웨어 다중 센서 신호 검증을 위한 패리티 공간 및 패턴인식 방법 (Parity Space and Pattern Recognition Approach for Hardware Redundant System Signal Validation using Artificial Neural Networks)

  • 윤태섭
    • 제어로봇시스템학회논문지
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    • 제4권6호
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    • pp.765-771
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    • 1998
  • An artificial neural network(NN) technique is developed for hardware redundant sensor validation. Since the measurement space is a continuous space with many operating regions, it is difficult to train a NN to correctly detect failure in an accurate measurement system. A conventional backpropagation NN is modified to include an additional preprocessing layer that extracts classification features from scalar measurements. This feature extraction means transform the measurement space to parity space. The NN is independent of the state variable being measured, the instrument range, and the signal tolerance. This NN resembles the parity space approach to signal validation, except that analytical parity equations are unneeded and the NN pattern recognition capability is utilized for decision making.

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차량 내 네트워크 통신의 기능안전성을 위한 하드웨어 기본 설계 (Basic Design of ECU Hardware for the Functional Safety of In-Vehicle Network Communication)

  • 곽현철;안현식
    • 전기학회논문지
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    • 제66권9호
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    • pp.1373-1378
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    • 2017
  • This paper presents a basic ECU(Electronic Control Unit) hardware development procedure for the functional safety of in-vehicle network systems. We consider complete hardware redundancy as a safety mechanism for in-vehicle communication network under the assumption of the wired network failure such as disconnection of a CAN bus. An ESC (Electronic Stability Control) system is selected as an item and the required ASIL(Automotive Safety Integrity Level) for this item is assigned by performing the HARA(Hazard Analysis and Risk Assessment). The basic hardware architecture of the ESC system is designed with a microcontroller, passive components, and communication transceivers. The required ASIL for ESC system is shown to be satisfied with the designed safety mechanism by calculation of hardware architecture metrics such as the SPFM(Single Point Fault Metric) and the LFM(Latent Fault Metric).

MI2U CONTROL FLIGHT SOFTWARE DESIGN AND DEVELOPMENT IN COMS

  • Kang, Seo-Yeon;Park, Su-Hyun;Koo, Cheol-Hae;Yang, Koon-Ho;Choi, Seong-Bong
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2006년도 Proceedings of ISRS 2006 PORSEC Volume I
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    • pp.271-273
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    • 2006
  • In this paper, we describe the MI2U ORB function which is a part of the flight software executed on SCU and controls MI2U/MI which is one of three payloads on COMS. The MI2U ORB function manages MI2U/MI redundancy and reconfiguration, monitors MI2U/MI equipment, performs FDIR, and provides the routing service of commands from Ground/IP (Interpreted Program) through the current used 1553 channel. The MI2U hardware achieves the interface between the SCU and the MI. The MI2U is connected to SCU through MIL-STD-1553B system bus. The MI2U has the internal redundancy but is used in cold redundancy. The MI2U ORB function considers that they are not expected to be simultaneously switched on. The connection combination between MI2U and MI is electrically cross-strapped. However the MI2U ORB function considers only two combinations (MI2U A + MI 1, MI2U B + MI 2). Other combinations can be manually achieved by ground in case of the emergency case.

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철도 신호 시스템을 위한 고장 허용 스위치드 이더넷 구조의 성능 평가 (Performance Evaluation of Fault Tolerant Switched Ethernet Architecture for Railway Signal System)

  • 황종규;이재호;조현정;김만호;박지훈;이경창;이석
    • 제어로봇시스템학회논문지
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    • 제12권12호
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    • pp.1241-1248
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    • 2006
  • In high reliability systems for industrial network such as railway signal system, fieldbus protocols have been known to satisfy the real-time and fault tolerant requirements. But, the application of fieldbus has been limited due to the high cost of hardware and software, and the difficulty in interfacing with multi-vendor products. Therefore, as an alternative to fieldbus, the computer network technology, especially Ethernet(IEEE 802.3), is being adapted to the industrial network. In this paper, we propose a switched Ethernet based railway signal system because of its very promising prospect for industrial application due to the elimination of uncertainties in the network operation. In addition, we propose the redundancy architecture for the reliability of network components. More specifically, this paper presents an analytical performance evaluation of switched Ethernet for railway signal system, and shows experimental evaluation of redundancy architecture.

원전 디지털 제어계통을 위한 고장허용설계방법론에 관한 연구 (A Study on Fault-Tolerance Design Methods for Nuclear Digital Control Systems)

  • 고원석;최중인
    • 대한전기학회논문지:시스템및제어부문D
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    • 제49권1호
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    • pp.1-9
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    • 2000
  • In this paper, a design method of fault-tolerance is presented for the nuclear digital control systems composed of software and hardware. As a quantitative design method measure of fault-tolerance, we used Reliability, Availability and Safety. To implement the proposed fault-tolerance, a prototype system has been devised for the digital control systems and a quantitative method of 'Markovian Model' is applied. The results provide the appropriate degree of redundancy and diversity, and fail-safe.

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High Repair Efficiency BIRA Algorithm with a Line Fault Scheme

  • Han, Tae-Woo;Jeong, Woo-Sik;Park, Young-Kyu;Kang, Sung-Ho
    • ETRI Journal
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    • 제32권4호
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    • pp.642-644
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    • 2010
  • With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.