• 한국IT서비스학회지
• /
• 제11권4호
• /
• pp.171-180
• /
• 2012

Since software and hardware integration has became a strategic tool for companies to innovate their products, an information system that can comprehensively manage software and hardware integrated product development is critical for the current product development. This paper proposed a product data model that can support modules of related software and hardware parts in Product Data Management(PDM) integrated with Software Configuration Management(SCM). The model allows engineers to define software and hardware product structure independently, and support the integration module that can summon related software and hardware parts to build a comprehensive module for collaboration. Through the integration module, engineers can identify and examine the effectiveness of their design alternatives to other related parts form different disciplines. The product data model was implemented as a prototype PDM system and tested with an example robotics product.

• 전기전자학회논문지
• /
• 제18권3호
• /
• pp.356-361
• /
• 2014

This paper proposes hardware architecture of HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) binarizer. The proposed binarizer was designed and implemented as an independent module that can be integrated into HEVC CABAC encoder. It generates each bin string of each syntax element in a single cycle. It consists of controller module, TU (truncated unary binarization) module, TR (truncated Rice binarization) module, FL (fixed length binarization) module, EGK (k-th order exp-Golomb coding) module, CALR (coeff_abs_level_remaining) module, QP Delta (cu_qp_delta_abs) module, Intra Pred (intra_chroma_pred_mode) module, Inter Pred (inter_pred_idc) module, and Part Mode (part_mode) module. The proposed binarizer was designed in Verilog HDL, and it was implemented in 45 nm technology. Its operating speed, gate count, and power consumption are 200 MHz, 1,678 gates, and 50 uW, respectively.

• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2004년도 춘계학술대회
• /
• pp.210-215
• /
• 2004

: A DNA analysis system based on fluorescence analysis has to have a DNA amplifying thermal cycle system. DNA amplification is executed by the temperature control. Accuracy of fluorescence analysis is influenced by the temperature control technology. For that reason, the temperature control is core technology in developing the DNA analysis system. Therefore, the objective of this paper is to develop the hardware to apply thermoelectric module to the DNA amplifying thermal cycle system. In order to verify the developed hardware for controlling the temperature of thermoelectric module, a DNA amplifying thermal cycle test was performed. From the test, the developed hardware controlled the temperature of thermoelectric module successfully. Therefore, it is expected that the developed hardware can be applied to the DNA amplifying thermal cycle system.

• 전기학회논문지
• /
• 제63권8호
• /
• pp.1046-1054
• /
• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• International Journal of Advanced Culture Technology
• /
• 제4권4호
• /
• pp.30-37
• /
• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• 한국통신학회논문지
• /
• 제13권2호
• /
• pp.171-181
• /
• 1988

본 논문에서는 packet-switched network에서 음성을 서비스하는데 있어서 고려해야 할 여러가지 점들을 살펴보고, 실제로 음성과 데이터를 동시에 서비스하는 packet voice/data terminal을 구현하였으며 그 성능 분석을 시도하였다. PVDT의 software는 OSI 7 layer architecture에 맞추어 설계하였으며 음성과 데이터를 link level부터 구별하여 서비스하였다. 또한 음성 packet의 전송 delay를 작게 하기 위해 데이터보다 음성을 우선적으로 서비스하도록 하였으며 간략화된 protocol로 재전송에 의한 overhead를 없앴다. PVDT의 hardware의 구성은 기능별로 master control module, speech processing module, speech activity detection module, telelphone interface module, input/output inteface module로 나누어진다. Packet음성통신망에 대한 해석으로는 음성 packet의 전송 delay의 variance에 의한 영향을 줄이기 위한 최적 재생지연시간을 전송 delay의 분포를 통해 계산하였다.

• ETRI Journal
• /
• 제25권5호
• /
• pp.328-336
• /
• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• 대한의용생체공학회:의공학회지
• /
• 제27권5호
• /
• pp.282-290
• /
• 2006

We have developed a multi band digital hearing aid algorithm emphasizing feedback cancellation and a hardware module to evaluate the performance of our algorithm. The hearing aids should be able to compensate for individual hearing loss characteristics of hearing impaired person. Thus hearing aids need the function of multi-bands amplification and the capabilities of feedback cancellation that can remove howling caused by acoustic feedback. In this paper, we proposed a digital hearing aid algorithm which has multi-bands compensation using modified discrete cosine transform (MDCT) and can efficiently remove acoustic feedbacks. Moreover, we have developed digital hearing aid hardware module, which can evaluate hearing aid algorithms in real time operation. The developed algorithm and hardware module were verified through computer simulation and clinical tests. Through operational experiments, good performances in real time operation environment and an efficient howling cancellation were also observed. The developed hardware module can operate in stable condition and it is expected to become a good hardware platform for developing hearing aid algorithms.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
• /
• pp.111-111
• /
• 2000

The research of network system, being used to reduce automotive wiring harness, is reaching to the development of by-wire system. It is by-wire system that apply IVN(In-Vehicle-Network) to steering, braking system, and it has the advantage of mass-decreasing, easy to diagnose fault and so on. But until now, many developed device can't satisfied with reliability that system have ever had. So redundancy of each network module, i.e., It is only way to make backup module. This paper researches development of network module and redundancy management of backup module when error occurred for implementation of brake-by-wire system.

• ETRI Journal
• /
• 제33권4호
• /
• pp.611-620
• /
• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.