• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.1
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• pp.34-41
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• 2002

In the conventional rake receiver structure for the IS-95 CDMA system, each finger has its own time-deskew buffer or FIFO that aligns the multipath signals to the same timing reference in order to combine symbols. This architecture is not a burden to the rake receiver design mainly because of the small number and size of the buffers. However, the number and size of the buffers are significantly increased in the cdma2000 system which adopts multiple carriers and the small spreading gain for a higher rate in data services. In order to decrease the number of buffers, we propose a new model of the time-deskew buffers, which combines the symbols as well as realigns them at the same time. Our architecture reduces the hardware complexity of the buffers by about more than 60% and 70% compared with the conventional one when we consider each rake receiver has three and four independent fingers, respectively. Moreover, the proposed algorithm is very useful not only to the cdma2000 rake receiver but also to the receiver with many fingers in order to increase the BER performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.9
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• pp.1-8
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• 2010

A digital phase wrapping modulation (DPM) open-loop polar transmitter can be efficiently applied to a wideband orthogonal frequency division multiplexing (OFDM) communication system by converting in-phase and quadrature signals to envelope and phase signals and then employing the signal mapping process. This mapping process is very similar to quantization in a general communication system, and when taking into account the error that appears during mapping process, one can replace the coordinates rotation digital computer (CORDIC) algorithm in the coordinate conversion part with the Taylor series approximation method. In this paper, we investigate the application of the Taylor series approximation to the cartesian to polar coordinate conversion part of a DPM polar transmitter for wideband OFDM systems. The conventional approach relies on the CORDIC algorithm. To achieve efficient application, we perform computer simulation to measure mean square error (MSE) of the both approaches and find the minimum approximation order for the Taylor series approximation compatible to allowable error of the CORDIC algorithm in terms of hardware design. Furthermore, comparing the processing speeds of the both approaches in the implementation with FPGA reveals that the Taylor series approximation with lower order improves the processing speed in the coordinate conversion part.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.100-110
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• 2001

In this paper, we investigated several buffer management schemes for the design of shared-memory type ATM switches, which can enhance the utilization of switch resources and can support quality-of-service (QoS) functionalities. Our results show that dynamic threshold (DT) scheme demonstrate a moderate degree of robustness close to pushout(PO) scheme, which is known to be impractical in the perspective of hardware implementation, under various traffic conditions such as traffic loads, burstyness of incoming traffic, and load non-uniformity across output ports. Next, we considered buffer management strategies to support QoS functions, which utilize parameter values obtained via connection admission control (CAC) procedures to set tile threshold values. Through simulations, we showed that the buffer management schemes adopted behave well in the sense that they can protect regulated traffic from unregulated cell traffic in allocating buffer space. In particular, it was observed that dynamic partitioning is superior in terms of QoS support than virtual partitioning.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• 대한공업교육학회지
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• v.41 no.2
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• pp.89-118
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• 2016

In this study, the model of Turtle Ship, which is evaluated as one of the world's first ironclad ship in battle as well as the traditional scientific and technological heritage in Korea, was combined with the Physical Computing Platform(Arduino and App Inventor) that enables students to learn the basic concepts of IT in an easy and fun way. Thus, this study contrived the Physical Computing Platform-based Turtle Ship model which will make the students of Industrial Specialized High School develop the technological literacy and humanities-based knowledge through flexible education out of stereotype and single subject as well as enhance the potential of creative convergence education. The following is a summary of the main results obtained through this study: First, Arduino-based Main-controller design and making is helpful to learn of the hardware and software knowledge about EEC(Electron Electronics Control) and to confirm the basic characteristics and performance of interaction of Arduino and actuators. Second, The fundamental Instructional environments of abilities such as implementing EEC systems, thinking logically, and problem-solving skills were provided by designing of pattern diagram, designing an actuator circuit and making, the creation of sketches as technical programming and developing of mobile app. Thirdly, This is physical computing platform based Turtle ship model that will enable students to bring up their technological literacy and interest in the cultural heritage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1113-1122
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• 2004

This paper is basically to achieve the high-availability and high-reliability of the control system from the implementation of the fault-tolerant system using the hot-standby sparing technique. To meet the objective, we design and implement a board with fault tolerance I/O bus to detect the fault. Warm-standby sparing technique is the fault tolerance technique usually used for switching control system in present. This technique can be easily implemented, but can not detect the fault quickly and can malfunction because of the hardware fault. The hot-standby sparing fault tolerant technique implemented in this paper is consists of dual processor modules and a I/O processor using fault tolerant I/O bus. The proposed method can find the faults as soon as possible, so it can prevent from wrong operation. Also it is possible to normal re-service due to the short recovering time. To implement the fault-tolerant dual system with fault detection be, two daughter, called FTMA and FTIA, boards designed and implemented are applied to the system. And we also simulated the proposed method to verify the high-availability and high-reliability of the control system using Markov process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8B
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• pp.668-676
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• 2012

In this paper, on the assumption that MPI collective communication function is converted into a group of point-to-point communication functions in the transaction level, an algorithm that optimizes broadcast, scatter and gather function among MPI collective communication is proposed. The MPI hardware engine that operates the proposed algorithm was designed, and it was named the OCC-MPE (Optimized Collective Communication Message Passing Engine). The OCC-MPE operates point-to-point communication by using the standard send mode. The transmission order is arranged according to the algorithm that proposes the most frequently used broadcast, scatter and gather functions among the collective communications, so the whole communication time is reduced. To measure the performance of the proposed algorithm, the OCC-MPE with the Bus Functional Model (BFM) based on SystemC was designed. After evaluating the performance through the BFM based on SystemC, the proposed OCC-MPE is designed by using VerilogHDL. As a result of synthesizing with the TSMC $0.18{\mu}m$, the gate count of each OCC-MPE is approximately 1978.95 with four processing nodes. That occupies approximately 4.15% in the whole system, which means it takes up a relatively small amount. Improved performance is expected with relatively small amounts of area increase if the OCC-MPE operated by the proposed algorithm is added to the MPSoC (Multi-Processor System on a Chip).

• Journal of IKEEE
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• v.19 no.4
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• pp.596-602
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• 2015

In this paper, a unified inverse transformer is designed for HEVC and VP9. The proposed architecture performs all modes of HEVC and VP9 in the unified inverser transformer, such as $4{\times}4{\sim}32{\times}32$ HEVC IDCT, $4{\times}4$ HEVC IDST, $4{\times}4{\sim}32{\times}32$ VP9 IDCT, $4{\times}4{\sim}16{\times}16$ VP9 IADST and $4{\times}4$ IWHT. Same computations are used in HEVC IDCT and VP9 IDCT, except for the scales of the coefficients. Similarly, same computations are used in HEVC $4{\times}4$ IDST and VP9 $4{\times}4$ IADST, except for the scales of the coefficients. Furthermore, HEVC IDCT, VP9 IDCT, and VP9 IADST are the subsets of upper level IDCTs. The proposed architecture reuses multipliers when the computation is identical. Also it shares adders and butterfly structures even when the multiplier coefficients are different. So it reduces the hardware size significantly. Synthesized in 0.18 um technology, the gate count is 456,442 gates. which achieved 22.6% reduction compared to conventional architectures.

• Journal of the Korea Society for Simulation
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• v.16 no.1
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• pp.11-19
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• 2007

Under ubiquitous environment, applications can gather and utilize various sensing information. There are many issues such as energy management, protocol standardization, independency on sensor fields, and security to be resolved for the complete ubiquitous computing. Especially, the independent information access in the sensor field is one of the most important issues to maximize the usability of sensors in various sensor fields. However, existing frameworks are not suitable for the ubiquitous computing environment because of data heterogeneity between data elements in sensor fields. Existing applications are dependent to sensor fields and sensors in the existing ubiquitous computing on environment is dependent to the application in the sensor field. In other word, an application can utilize just information from a specific sensor field. To overcome this restriction, many issues from a hardware or software view must be resolved. In this paper, we provide the design and implementation of the Metadata Registry-based framework (UbiMDR) of the Ubiquitous environment. This framework can provides the semantic interoperability among ubiquitous applications or various sensor fields. In addition, we describe comparison evaluation between conventional Ubiquitous computing framework and UbiMDR framework with data accuracy of interoperability.