• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.363-366
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• 2007

This paper evaluated the performance of circuit for compensate the frequency offset in OFDM using Simulink and designed a System Generator model for FPGA implementation. System Generator Model generated HDL code and RTL schematic. Also, evaluate the performance through Hardware Co-simulation, and investigated the result of timing analysis and resource estimation.

• Journal of Biosystems Engineering
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• v.37 no.3
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• pp.148-154
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• 2012

Purpose: In order to improve road-friendliness of heavy vehicles, a fuzzy hybrid control strategy consisting of a hybrid control strategy and a fuzzy logic control module is proposed. The performance of the proposed strategy should be effectively evaluated using a hardware-in-the-loop (HIL) simulation model of a semi-active suspension system based on the fuzzy hybrid control strategy prior to real vehicle implementations. Methods: A hardware-in-the-loop (HIL) simulation system was synthesized by utilizing a self-developed electronic control unit (ECU), a PCI-1711 multi-functional data acquisition board as well as the previously developed quarter-car simulation model. Road-friendliness of a semi-active suspension system controlled by the proposed control strategy was simulated via the HIL system using Dynamic Load Coefficient (DLC) and Dynamic Load Stress Factor (DLSF) criteria. Results: Compared to a passive suspension, a semi-active suspension system based on the fuzzy hybrid control strategy reduced the DLC and DLSF values. Conclusions: The proposed control strategy of semi-active suspension systems can be employed to improve road-friendliness of road vehicles.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.336-339
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• 2007

A chaos signal is used in all fields like engineering, a medical science and a biology very much, and study regarding the digital communication system that used a recent chaos signal is consisting actively. Applied a chaos signal in a digital communication system, and this paper designed six chaos signal generator to have been composed of by nonlinear equations as used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of six chaos generator.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.05a
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• pp.1-7
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• 2001

본 논문에서는 UML의 배치 다이어그램이 가지는 런타임 아키텍쳐 정보를 통해 시뮬레이션 모델을 구성하고, 이 모델을 실제 시뮬레이션하여 구현 단계 이전에 시스템 아키텍쳐의 유효성과 성능 정보를 검토하는 CoSim(Hardware Software Co-Simulator System)을 제시한다. CoSim은 자바빈즈 컴포넌트 기반으로, 크게 Modeler, Translator, Scenario로 구성된다. 시스템 개발자는 Modeler를 이용하여 시뮬레이션 모델을 작성하며, Translator는 모델에 대한 시뮬레이션 자바 코드를 생성하고, 그 결과물을 바탕으로 Scenario는 비주얼한 정보를 제공한다. 따라서 모델이 실제 플랫폼 상에서 작동되기 이전에 아키텍쳐 성능에 관련된 유용한 정보를 제공하여 개발 위험도를 감소시키고 비용의 절감을 가져 올 수 있다. CoSim은 Modeler, Translator, Scenario 별로 자바빈즈 컴포넌트 라이브러리를 제공함으로써 모델링의 재사용성과 확장성 및 생산성을 높여 줄 수 있다.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10b
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• pp.1028-1032
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• 1988

The purpose of this paper is the development of a fully integrated simulation package for industrial robot. The simulation package consists of kinematics, dynamics, and control. The kinematics contains trajectory plans and inverse kinematics. The dynamics combines manipulator dynamics and actuator dynamics including the effect of payloads and viscous frictions. The control is a hardware oriented scheme which contains position controller, velocity controller, current controller, and PWM generator. Thus, the simulation package can be used not only for theoretical purposes but also for development purposes in industry. Using this package, the characteristics and performances of the SCARA robot, which has been developed in GSIS, are investigated.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.10
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• pp.829-839
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• 2021

Autonomous system for UAVs has a capability to decide an appropriate current action to achieve the goal based on the ultimate mission goal, context of mission, and the current state of the UAV. We propose a decision-making system that has an ability to operate ISR mission autonomously under the realistic limitation such as low altitude operation with high risk of terrain collision, a set of way points without change of visit sequence not allowed, and position uncertainties of the objects for the mission. The proposed decision-making system is loaded to a Hardware-In-the-loop Simulation environment, then tested and verified using three representative scenarios with a realistic mission environment. The flight trajectories of the UAV and selected actions via the proposed decision-making system are presented as the simulation results with discussion.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1803-1810
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• 2009

This paper designed IQ imbalance estimator and compensator to cancel the IQ imbalance error in DVB-T system using OFDM by Matlab. Among Matlab model, we designed and implemented IQ imbalance estimator and compensator by System Generator of Xilinx and Matlab model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model estimated and compensated IQ imbalance error very well. Also, we verified the performance through hardware co-simulation, timing analysis and resource estimation with Xilinx Spartan3 xc3s1000 fg676-4 target Device.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.779-781
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• 2007

Nowadays, as the increasing functionality and scales of embedded systems, system design grows more complex than before. So verification and simulation of systems become an important facet in hardware-software co-design issues. But it is almost impossible to simulate an embedded system without real hardware implementation or environment communication, especially for control-dominated reactive systems. Therefore, in this paper, we will introduce a GUI environment module generator for integrated Esterel\C++ simulation. By generating the GUI modeling environment, we can simulate and verify the whole embedded system conveniently.