• 제목/요약/키워드: Hardware Test

검색결과 1,066건 처리시간 0.026초

분할 및 병렬 처리 방법에 의한 BIST의 테스트 시간 감소 (Test Time Reduction for BIST by Parallel Divide-and-Conquer Method)

  • 최병구;김동욱
    • 대한전기학회논문지:시스템및제어부문D
    • /
    • 제49권6호
    • /
    • pp.322-329
    • /
    • 2000
  • BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

  • PDF

이종센서 영상탐색기 시험평가를 위한 적외선 표적원 개발 (Development of Infrared Target for Dual-Sensor Imaging Seeker's Test and Evaluation in HILS System)

  • 박장한;송성찬;정상원
    • 한국전자파학회논문지
    • /
    • 제29권11호
    • /
    • pp.898-905
    • /
    • 2018
  • 본 논문에서는 대지, 대공 표적을 포착 추적할 수 있는 적외선 및 가시광 센서가 탑재된 이종센서 영상탐색기의 종합 성능시험을 위해 구축한 HILS(Hardware In-the-Loop Simulation) 시스템 내에 적외선 표적원을 제안한다. 이 통합시스템은 다양한 종류의 표적과 시나리오 기반 이동 표적의 궤적을 모사하기 위해 열원 및 광원을 출력하는 100개의 모듈로 구성하였다. 또한 표적에 대한 위치, 속도, 방향, 배경 클러터와 재밍 환경 등을 모사할 수 있다. 이종센서 영상탐색기의 시험평가를 위해 구축된 HILS 시스템의 전체 시스템 구성과 적외선 표적원의 설계 및 측정 결과를 제시한다. 향후에, 구축된 HILS 시스템에서 모의비행 시나리오 기반으로 동적 실시간 포착 추적에 대한 단일 또는 이종센서가 탑재된 이종센서 영상탐색기의 성능을 시험할 예정이다.

Gluster 파일시스템을 이용한 상관자료 수집 시스템 구축 및 시험고찰 (A Study on the Test Results and Implementation of Correlated Result Saving System using the Gluster File System)

  • 염재환;오세진;노덕규;정동규;황주연;오충식;김효령
    • 융합신호처리학회논문지
    • /
    • 제17권2호
    • /
    • pp.53-60
    • /
    • 2016
  • 본 논문에서는 대전상관기의 전체 성능을 달성하기 위해 새로운 방식의 상관자료 수집장치의 구축과 시험결과에 대해 소개한다. 최근 한국우주전파관측망(Korean VLBI Network, KVN)의 최대 관측규격인 8Gbps 속도의 관측이 수행되고 있으며, 대전상관기를 이용한 상관처리도 요구되고 있기 때문에 노후 장치를 대체하여 최대 상관처리 속도에 대응하기 위한 새로운 상관자료 수집장치의 도입이 필요하게 되었다. 대전상관기의 최대 상관결과 출력속도는 25.6ms 적분시간에 대해 초당 1.4GB/sec이다. 기존에 도입한 상관자료 수집장치는 대전상관기의 최대 상관출력 속도에 대응하지 못해 출력속도를 1/4로 제한하여 활용되었다. 즉, 대전상관기의 입력포트 4개 중에 관측속도 1Gbps에만 대응하도록 3개의 입력은 제한하였다. 이번에 도입한 장치는 스토리지 시스템에서 활용되고 있는 여러 최신의 기술 중에서 Gluster 파일 시스템을 사용하고 있으며, 대전상관기의 최대 출력속도인 1.4GB/sec를 만족하는 시험에서 광 출력 4개에 대해 각각 350MB/sec, 총 1.4GB/sec의 결과를 얻었다.

A Twin Symbol Encoding Technique Based on Run-Length for Efficient Test Data Compression

  • Park, Jae-Seok;Kang, Sung-Ho
    • ETRI Journal
    • /
    • 제33권1호
    • /
    • pp.140-143
    • /
    • 2011
  • Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

Trade-off Study on the Performance of GPS/INS for Aviation Navigation

  • Changsun Yoo;leeki Ahn;Lee, Sangjeong
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 제어로봇시스템학회 2002년도 ICCAS
    • /
    • pp.47.2-47
    • /
    • 2002
  • $\textbullet$ Introduction of aviation navigation $\textbullet$ Integrated navigation algorithm $\textbullet$ Description of hardware system $\textbullet$ Ground test $\textbullet$ Flight test $\textbullet$ Conclusion

  • PDF

Improvement of Defect Detection in TFT-Array Panel

  • Chung, Kyo-Young
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
    • /
    • pp.594-597
    • /
    • 2005
  • This paper shows that the defect detection in TFTarray panel can be improved by using newly developed software solution without adding additional hardware instruments. Some issues are reviewed in current TFT array test and new algorithm is explained for detecting more real defects without paying the penalty of reporting more false defects in TFT array test.

  • PDF

Hardware Co-Simulation of an Adaptive Field Oriented Control of Induction Motor

  • Kabache, Nadir;Moulahoum, Samir;Houassine, Hamza
    • Journal of international Conference on Electrical Machines and Systems
    • /
    • 제3권2호
    • /
    • pp.110-115
    • /
    • 2014
  • The reconfigurability of FPGA devices allows designers to evaluate, test and validate a new control algorithm; a new component or prototypes without damaged the real system with the so-called hardware co-simulation. The present paper uses the Xilinx System Generator (XSG) environment to establish and validate a new nonlinear estimator for the rotor time constant inverse that will be exploited to improve the indirect rotor field control of induction motor.

ABS를 위한 HIL시뮬레이터 개발 (Development of Hardware-In-The-Loop Simulator for ABS)

  • 서명원;김석민;정재현;석창성;김영진;이선일;이재천
    • 한국자동차공학회논문집
    • /
    • 제6권2호
    • /
    • pp.155-167
    • /
    • 1998
  • The prevalence of microprocessor-based controllers in automotive systems has greatly increased the meed for tools which can be used to validate and test control systems over their full range of operation. The objective of this paper is to develop a real time simulator of an anti-lock braking system and the methodology of using hardware-in-the-loop simulation based on a personal computer. By use of this simulator, the analyses of a commercial electronic control unit as well as the validation of the developed control logics for ABS were performed successfully. The simulator of this research can be traction applied to development of more advanced control system, such as traction control systems, vehicle dynamic control system and so forth.

  • PDF

차간거리 경보시스템의 HiLS 구현 (An Experimental Investigation of a Collision Warning System for Automobiles using Hardware-in-the-Loop Simulations)

  • 송철기;김성하;이경수
    • 한국자동차공학회논문집
    • /
    • 제6권5호
    • /
    • pp.222-227
    • /
    • 1998
  • Collision warning systems have been an active research and development area as the interests and demands for ASV's (Advanced Safety Vehicles) have increased. This paper presents an experimental investigation of a collision warning system for automobiles. A collision warning HiLS(Hardware-in-the-Loop Simulation) system has been designed and used to test the collision warning algorithm, radar sensors, and warning displays under realistic operating conditions in the laboratory. the collision warning algorithm is operated by a warning index, which is a function of the warning distance and the braking distance. The computer calculates velocities of the preceding vehicle and following vehicle, relative distance and relative velocity of the vehicles using vehicle simulation models. The relative distance and the relative velocity are applied to the vehicle simulator controlled by a DC motor.

  • PDF